From a944a8eba93f771d7b7fe8a7271ff0dd59f67b58 Mon Sep 17 00:00:00 2001 From: Karol Herbst Date: Tue, 18 Jul 2023 22:22:43 +0200 Subject: [PATCH] nvc0: initial Ada enablement Cc: 23.2 Signed-off-by: Karol Herbst Reviewed-by: M Henning Part-of: --- src/gallium/drivers/nouveau/nv_object.xml.h | 2 ++ src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 3 +++ src/gallium/winsys/nouveau/drm/nouveau_drm_winsys.c | 1 + src/nouveau/codegen/nv50_ir_ra.cpp | 2 ++ src/nouveau/codegen/nv50_ir_target.cpp | 1 + 5 files changed, 9 insertions(+) diff --git a/src/gallium/drivers/nouveau/nv_object.xml.h b/src/gallium/drivers/nouveau/nv_object.xml.h index 7931096..f062807 100644 --- a/src/gallium/drivers/nouveau/nv_object.xml.h +++ b/src/gallium/drivers/nouveau/nv_object.xml.h @@ -198,6 +198,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GV100_3D_CLASS 0x0000c397 #define TU102_3D_CLASS 0x0000c597 #define GA102_3D_CLASS 0x0000c797 +#define AD102_3D_CLASS 0x0000c997 #define NV50_2D_CLASS 0x0000502d #define NVC0_2D_CLASS 0x0000902d #define NV50_COMPUTE_CLASS 0x000050c0 @@ -213,6 +214,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GV100_COMPUTE_CLASS 0x0000c3c0 #define TU102_COMPUTE_CLASS 0x0000c5c0 #define GA102_COMPUTE_CLASS 0x0000c7c0 +#define AD102_COMPUTE_CLASS 0x0000c9c0 #define NV84_CRYPT_CLASS 0x000074c1 #define BLOB_NVC0_PCOPY1_CLASS 0x000090b8 #define BLOB_NVC0_PCOPY0_CLASS 0x000090b5 diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c index 776430e..b7e603a 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c @@ -790,6 +790,7 @@ static int nvc0_screen_init_compute(struct nvc0_screen *screen) { const struct nouveau_mclass computes[] = { + { AD102_COMPUTE_CLASS, -1 }, { GA102_COMPUTE_CLASS, -1 }, { TU102_COMPUTE_CLASS, -1 }, { GV100_COMPUTE_CLASS, -1 }, @@ -981,6 +982,7 @@ nvc0_screen_create(struct nouveau_device *dev) case 0x140: case 0x160: case 0x170: + case 0x190: break; default: return NULL; @@ -1129,6 +1131,7 @@ nvc0_screen_create(struct nouveau_device *dev) PUSH_DATA (push, screen->fence.bo->offset + 16); const struct nouveau_mclass threeds[] = { + { AD102_3D_CLASS, -1 }, { GA102_3D_CLASS, -1 }, { TU102_3D_CLASS, -1 }, { GV100_3D_CLASS, -1 }, diff --git a/src/gallium/winsys/nouveau/drm/nouveau_drm_winsys.c b/src/gallium/winsys/nouveau/drm/nouveau_drm_winsys.c index 516c44a..584acf75 100644 --- a/src/gallium/winsys/nouveau/drm/nouveau_drm_winsys.c +++ b/src/gallium/winsys/nouveau/drm/nouveau_drm_winsys.c @@ -109,6 +109,7 @@ nouveau_drm_screen_create(int fd) case 0x140: case 0x160: case 0x170: + case 0x190: init = nvc0_screen_create; break; default: diff --git a/src/nouveau/codegen/nv50_ir_ra.cpp b/src/nouveau/codegen/nv50_ir_ra.cpp index bf0ff23..bf7d850 100644 --- a/src/nouveau/codegen/nv50_ir_ra.cpp +++ b/src/nouveau/codegen/nv50_ir_ra.cpp @@ -1062,6 +1062,7 @@ GCRA::coalesce(ArrayList& insns) case 0x140: case 0x160: case 0x170: + case 0x190: ret = doCoalesce(insns, JOIN_MASK_UNION); break; default: @@ -2566,6 +2567,7 @@ RegAlloc::InsertConstraintsPass::visit(BasicBlock *bb) case 0x140: case 0x160: case 0x170: + case 0x190: texConstraintGM107(tex); break; default: diff --git a/src/nouveau/codegen/nv50_ir_target.cpp b/src/nouveau/codegen/nv50_ir_target.cpp index f0eb807..f4464da 100644 --- a/src/nouveau/codegen/nv50_ir_target.cpp +++ b/src/nouveau/codegen/nv50_ir_target.cpp @@ -154,6 +154,7 @@ Target *Target::create(unsigned int chipset) STATIC_ASSERT(ARRAY_SIZE(operationSrcNr) == OP_LAST + 1); STATIC_ASSERT(ARRAY_SIZE(operationClass) == OP_LAST + 1); switch (chipset & ~0xf) { + case 0x190: case 0x170: case 0x160: case 0x140: -- 2.7.4