From a91c40285fe5803cea9b4be652d4991a6d4f820c Mon Sep 17 00:00:00 2001 From: Ruiling Song Date: Thu, 29 May 2014 10:29:34 +0800 Subject: [PATCH] GBE: Pass correct register type when replaceReg Signed-off-by: Ruiling Song Reviewed-by: "Yang, Rong R" --- backend/src/backend/gen_insn_selection.cpp | 17 +++++++++++++++++ backend/src/backend/gen_insn_selection.hpp | 2 ++ backend/src/backend/gen_reg_allocation.cpp | 3 ++- 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp index 7060240..9886357 100644 --- a/backend/src/backend/gen_insn_selection.cpp +++ b/backend/src/backend/gen_insn_selection.cpp @@ -129,6 +129,23 @@ namespace gbe } } + ir::Type getIRType(uint32_t genType) { + using namespace ir; + switch (genType) { + case GEN_TYPE_B: return TYPE_S8; + case GEN_TYPE_UB: return TYPE_U8; + case GEN_TYPE_W: return TYPE_S16; + case GEN_TYPE_UW: return TYPE_U16; + case GEN_TYPE_D: return TYPE_S32; + case GEN_TYPE_UD: return TYPE_U32; + case GEN_TYPE_L: return TYPE_S64; + case GEN_TYPE_UL: return TYPE_U64; + case GEN_TYPE_F: return TYPE_FLOAT; + case GEN_TYPE_DF: return TYPE_DOUBLE; + default: NOT_SUPPORTED; return TYPE_FLOAT; + } + } + uint32_t getGenCompare(ir::Opcode opcode, bool inverse = false) { using namespace ir; switch (opcode) { diff --git a/backend/src/backend/gen_insn_selection.hpp b/backend/src/backend/gen_insn_selection.hpp index 0140a63..508a37e 100644 --- a/backend/src/backend/gen_insn_selection.hpp +++ b/backend/src/backend/gen_insn_selection.hpp @@ -38,6 +38,8 @@ namespace gbe { /*! Translate IR type to Gen type */ uint32_t getGenType(ir::Type type); + /*! Translate Gen type to IR type */ + ir::Type getIRType(uint32_t genType); /*! Translate IR compare to Gen compare */ uint32_t getGenCompare(ir::Opcode opcode); diff --git a/backend/src/backend/gen_reg_allocation.cpp b/backend/src/backend/gen_reg_allocation.cpp index db65851..d225bdb 100644 --- a/backend/src/backend/gen_reg_allocation.cpp +++ b/backend/src/backend/gen_reg_allocation.cpp @@ -316,7 +316,8 @@ namespace gbe // the MOVs else { ir::Register tmp; - tmp = this->replaceReg(selection, vector->insn, regID, vector->isSrc); + ir::Type type = getIRType(vector->reg[regID].type); + tmp = this->replaceReg(selection, vector->insn, regID, vector->isSrc, type); const VectorLocation location = std::make_pair(vector, regID); this->vectorMap.insert(std::make_pair(tmp, location)); } -- 2.7.4