From a90e5a8f0d010c339e4f14e0b098a2a147ef8e67 Mon Sep 17 00:00:00 2001
From: Fangrui Song <i@maskray.me>
Date: Wed, 30 Dec 2020 15:26:09 -0800
Subject: [PATCH] [SystemZ][test] Add explicit dso_local to definitions in ELF
 static relocation model tests

---
 llvm/test/CodeGen/SystemZ/and-08.ll      | 62 +++++++++++++-------------
 llvm/test/CodeGen/SystemZ/branch-06.ll   | 24 +++++-----
 llvm/test/CodeGen/SystemZ/int-cmp-36.ll  | 16 +++----
 llvm/test/CodeGen/SystemZ/int-cmp-37.ll  | 16 +++----
 llvm/test/CodeGen/SystemZ/int-cmp-38.ll  | 18 ++++----
 llvm/test/CodeGen/SystemZ/int-cmp-39.ll  | 16 +++----
 llvm/test/CodeGen/SystemZ/int-cmp-40.ll  | 16 +++----
 llvm/test/CodeGen/SystemZ/int-cmp-41.ll  | 16 +++----
 llvm/test/CodeGen/SystemZ/int-cmp-42.ll  | 16 +++----
 llvm/test/CodeGen/SystemZ/int-cmp-43.ll  | 16 +++----
 llvm/test/CodeGen/SystemZ/int-move-08.ll | 40 ++++++++---------
 llvm/test/CodeGen/SystemZ/int-move-09.ll | 52 +++++++++++-----------
 llvm/test/CodeGen/SystemZ/int-move-10.ll | 46 +++++++++----------
 llvm/test/CodeGen/SystemZ/la-01.ll       | 26 +++++------
 llvm/test/CodeGen/SystemZ/memcpy-02.ll   | 76 ++++++++++++++++----------------
 llvm/test/CodeGen/SystemZ/pie.ll         |  4 +-
 llvm/test/CodeGen/SystemZ/prefetch-01.ll | 18 ++++----
 llvm/test/CodeGen/SystemZ/spill-01.ll    | 64 +++++++++++++--------------
 llvm/test/CodeGen/SystemZ/tls-01.ll      |  4 +-
 19 files changed, 273 insertions(+), 273 deletions(-)

diff --git a/llvm/test/CodeGen/SystemZ/and-08.ll b/llvm/test/CodeGen/SystemZ/and-08.ll
index ad5351f..4b3d83bd 100644
--- a/llvm/test/CodeGen/SystemZ/and-08.ll
+++ b/llvm/test/CodeGen/SystemZ/and-08.ll
@@ -2,13 +2,13 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
-@g1src = global i8 1
-@g1dst = global i8 1
-@g2src = global i16 2
-@g2dst = global i16 2
+@g1src = dso_local global i8 1
+@g1dst = dso_local global i8 1
+@g2src = dso_local global i16 2
+@g2dst = dso_local global i16 2
 
 ; Test the simple i8 case.
-define void @f1(i8 *%ptr1) {
+define dso_local void @f1(i8 *%ptr1) {
 ; CHECK-LABEL: f1:
 ; CHECK: nc 1(1,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -21,7 +21,7 @@ define void @f1(i8 *%ptr1) {
 }
 
 ; ...and again in reverse.
-define void @f2(i8 *%ptr1) {
+define dso_local void @f2(i8 *%ptr1) {
 ; CHECK-LABEL: f2:
 ; CHECK: nc 1(1,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -35,7 +35,7 @@ define void @f2(i8 *%ptr1) {
 
 ; Test i8 cases where one value is zero-extended to 32 bits and the other
 ; sign-extended.
-define void @f3(i8 *%ptr1) {
+define dso_local void @f3(i8 *%ptr1) {
 ; CHECK-LABEL: f3:
 ; CHECK: nc 1(1,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -51,7 +51,7 @@ define void @f3(i8 *%ptr1) {
 }
 
 ; ...and again with the extension types reversed.
-define void @f4(i8 *%ptr1) {
+define dso_local void @f4(i8 *%ptr1) {
 ; CHECK-LABEL: f4:
 ; CHECK: nc 1(1,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -67,7 +67,7 @@ define void @f4(i8 *%ptr1) {
 }
 
 ; ...and again with two sign extensions.
-define void @f5(i8 *%ptr1) {
+define dso_local void @f5(i8 *%ptr1) {
 ; CHECK-LABEL: f5:
 ; CHECK: nc 1(1,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ define void @f5(i8 *%ptr1) {
 }
 
 ; ...and again with two zero extensions.
-define void @f6(i8 *%ptr1) {
+define dso_local void @f6(i8 *%ptr1) {
 ; CHECK-LABEL: f6:
 ; CHECK: nc 1(1,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -100,7 +100,7 @@ define void @f6(i8 *%ptr1) {
 
 ; Test i8 cases where the value is extended to 64 bits (just one case
 ; this time).
-define void @f7(i8 *%ptr1) {
+define dso_local void @f7(i8 *%ptr1) {
 ; CHECK-LABEL: f7:
 ; CHECK: nc 1(1,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -116,7 +116,7 @@ define void @f7(i8 *%ptr1) {
 }
 
 ; Test the simple i16 case.
-define void @f8(i16 *%ptr1) {
+define dso_local void @f8(i16 *%ptr1) {
 ; CHECK-LABEL: f8:
 ; CHECK: nc 2(2,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -129,7 +129,7 @@ define void @f8(i16 *%ptr1) {
 }
 
 ; Test i16 cases where the value is extended to 32 bits.
-define void @f9(i16 *%ptr1) {
+define dso_local void @f9(i16 *%ptr1) {
 ; CHECK-LABEL: f9:
 ; CHECK: nc 2(2,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -145,7 +145,7 @@ define void @f9(i16 *%ptr1) {
 }
 
 ; Test i16 cases where the value is extended to 64 bits.
-define void @f10(i16 *%ptr1) {
+define dso_local void @f10(i16 *%ptr1) {
 ; CHECK-LABEL: f10:
 ; CHECK: nc 2(2,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -161,7 +161,7 @@ define void @f10(i16 *%ptr1) {
 }
 
 ; Test the simple i32 case.
-define void @f11(i32 *%ptr1) {
+define dso_local void @f11(i32 *%ptr1) {
 ; CHECK-LABEL: f11:
 ; CHECK: nc 4(4,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -174,7 +174,7 @@ define void @f11(i32 *%ptr1) {
 }
 
 ; Test i32 cases where the value is extended to 64 bits.
-define void @f12(i32 *%ptr1) {
+define dso_local void @f12(i32 *%ptr1) {
 ; CHECK-LABEL: f12:
 ; CHECK: nc 4(4,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -190,7 +190,7 @@ define void @f12(i32 *%ptr1) {
 }
 
 ; Test the i64 case.
-define void @f13(i64 *%ptr1) {
+define dso_local void @f13(i64 *%ptr1) {
 ; CHECK-LABEL: f13:
 ; CHECK: nc 8(8,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -203,7 +203,7 @@ define void @f13(i64 *%ptr1) {
 }
 
 ; Make sure that we don't use NC if the first load is volatile.
-define void @f14(i64 *%ptr1) {
+define dso_local void @f14(i64 *%ptr1) {
 ; CHECK-LABEL: f14:
 ; CHECK-NOT: nc
 ; CHECK: br %r14
@@ -216,7 +216,7 @@ define void @f14(i64 *%ptr1) {
 }
 
 ; ...likewise the second.
-define void @f15(i64 *%ptr1) {
+define dso_local void @f15(i64 *%ptr1) {
 ; CHECK-LABEL: f15:
 ; CHECK-NOT: nc
 ; CHECK: br %r14
@@ -229,7 +229,7 @@ define void @f15(i64 *%ptr1) {
 }
 
 ; ...likewise the store.
-define void @f16(i64 *%ptr1) {
+define dso_local void @f16(i64 *%ptr1) {
 ; CHECK-LABEL: f16:
 ; CHECK-NOT: nc
 ; CHECK: br %r14
@@ -244,7 +244,7 @@ define void @f16(i64 *%ptr1) {
 ; Test that NC is not used for aligned loads and stores if there is
 ; no way of telling whether they alias.  We don't want to use NC in
 ; cases where the addresses could be equal.
-define void @f17(i64 *%ptr1, i64 *%ptr2) {
+define dso_local void @f17(i64 *%ptr1, i64 *%ptr2) {
 ; CHECK-LABEL: f17:
 ; CHECK-NOT: nc
 ; CHECK: br %r14
@@ -256,7 +256,7 @@ define void @f17(i64 *%ptr1, i64 *%ptr2) {
 }
 
 ; ...but if one of the loads isn't aligned, we can't be sure.
-define void @f18(i64 *%ptr1, i64 *%ptr2) {
+define dso_local void @f18(i64 *%ptr1, i64 *%ptr2) {
 ; CHECK-LABEL: f18:
 ; CHECK-NOT: nc
 ; CHECK: br %r14
@@ -268,7 +268,7 @@ define void @f18(i64 *%ptr1, i64 *%ptr2) {
 }
 
 ; Repeat the previous test with the operands in the opposite order.
-define void @f19(i64 *%ptr1, i64 *%ptr2) {
+define dso_local void @f19(i64 *%ptr1, i64 *%ptr2) {
 ; CHECK-LABEL: f19:
 ; CHECK-NOT: nc
 ; CHECK: br %r14
@@ -280,7 +280,7 @@ define void @f19(i64 *%ptr1, i64 *%ptr2) {
 }
 
 ; ...and again with the other operand being unaligned.
-define void @f20(i64 *%ptr1, i64 *%ptr2) {
+define dso_local void @f20(i64 *%ptr1, i64 *%ptr2) {
 ; CHECK-LABEL: f20:
 ; CHECK-NOT: nc
 ; CHECK: br %r14
@@ -292,7 +292,7 @@ define void @f20(i64 *%ptr1, i64 *%ptr2) {
 }
 
 ; Test a case where there is definite overlap.
-define void @f21(i64 %base) {
+define dso_local void @f21(i64 %base) {
 ; CHECK-LABEL: f21:
 ; CHECK-NOT: nc
 ; CHECK: br %r14
@@ -307,7 +307,7 @@ define void @f21(i64 %base) {
 }
 
 ; Test that we can use NC for global addresses for i8.
-define void @f22(i8 *%ptr) {
+define dso_local void @f22(i8 *%ptr) {
 ; CHECK-LABEL: f22:
 ; CHECK-DAG: larl [[SRC:%r[0-5]]], g1src
 ; CHECK-DAG: larl [[DST:%r[0-5]]], g1dst
@@ -321,7 +321,7 @@ define void @f22(i8 *%ptr) {
 }
 
 ; Test that we use NC even where LHRL and STHRL are available.
-define void @f23(i16 *%ptr) {
+define dso_local void @f23(i16 *%ptr) {
 ; CHECK-LABEL: f23:
 ; CHECK-DAG: larl [[SRC:%r[0-5]]], g2src
 ; CHECK-DAG: larl [[DST:%r[0-5]]], g2dst
@@ -335,7 +335,7 @@ define void @f23(i16 *%ptr) {
 }
 
 ; Test a case where offset disambiguation is enough.
-define void @f24(i64 *%ptr1) {
+define dso_local void @f24(i64 *%ptr1) {
 ; CHECK-LABEL: f24:
 ; CHECK: nc 8(8,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -348,7 +348,7 @@ define void @f24(i64 *%ptr1) {
 }
 
 ; Test a case where TBAA tells us there is no alias.
-define void @f25(i64 *%ptr1, i64 *%ptr2) {
+define dso_local void @f25(i64 *%ptr1, i64 *%ptr2) {
 ; CHECK-LABEL: f25:
 ; CHECK: nc 0(8,%r3), 0(%r2)
 ; CHECK: br %r14
@@ -360,7 +360,7 @@ define void @f25(i64 *%ptr1, i64 *%ptr2) {
 }
 
 ; Test a case where TBAA information is present but doesn't help.
-define void @f26(i64 *%ptr1, i64 *%ptr2) {
+define dso_local void @f26(i64 *%ptr1, i64 *%ptr2) {
 ; CHECK-LABEL: f26:
 ; CHECK-NOT: nc
 ; CHECK: br %r14
@@ -373,7 +373,7 @@ define void @f26(i64 *%ptr1, i64 *%ptr2) {
 
 ; Test a case where one of the loads are optimized by the DAGCombiner to a
 ; zero-extending load of half the original size.
-define void @f27(i16* noalias %ptr1, i16* noalias %ptr2) {
+define dso_local void @f27(i16* noalias %ptr1, i16* noalias %ptr2) {
 ; CHECK-LABEL: f27:
 ; CHECK-NOT: nc
 ; CHECK: br %r14
diff --git a/llvm/test/CodeGen/SystemZ/branch-06.ll b/llvm/test/CodeGen/SystemZ/branch-06.ll
index 1bc5fd1..bb83d31 100644
--- a/llvm/test/CodeGen/SystemZ/branch-06.ll
+++ b/llvm/test/CodeGen/SystemZ/branch-06.ll
@@ -3,9 +3,9 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 declare i32 @foo()
-@g1 = global i16 0
+@g1 = dso_local global i16 0
 
-define void @f1(i32 %target) {
+define dso_local void @f1(i32 %target) {
 ; CHECK-LABEL: f1:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
@@ -19,7 +19,7 @@ exit:
   ret void
 }
 
-define void @f2(i32 %target) {
+define dso_local void @f2(i32 %target) {
 ; CHECK-LABEL: f2:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
@@ -33,7 +33,7 @@ exit:
   ret void
 }
 
-define void @f3(i32 %target) {
+define dso_local void @f3(i32 %target) {
 ; CHECK-LABEL: f3:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
@@ -47,7 +47,7 @@ exit:
   ret void
 }
 
-define void @f4(i32 %target) {
+define dso_local void @f4(i32 %target) {
 ; CHECK-LABEL: f4:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
@@ -61,7 +61,7 @@ exit:
   ret void
 }
 
-define void @f5(i32 %target) {
+define dso_local void @f5(i32 %target) {
 ; CHECK-LABEL: f5:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
@@ -75,7 +75,7 @@ exit:
   ret void
 }
 
-define void @f6(i32 %target) {
+define dso_local void @f6(i32 %target) {
 ; CHECK-LABEL: f6:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
@@ -91,7 +91,7 @@ exit:
 
 ; Check that CRJ is used for checking equality with a zero-extending
 ; character load.
-define void @f7(i8 *%targetptr) {
+define dso_local void @f7(i8 *%targetptr) {
 ; CHECK-LABEL: f7:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
@@ -109,7 +109,7 @@ exit:
 }
 
 ; ...and zero-extending i16 loads.
-define void @f8(i16 *%targetptr) {
+define dso_local void @f8(i16 *%targetptr) {
 ; CHECK-LABEL: f8:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
@@ -127,7 +127,7 @@ exit:
 }
 
 ; ...unless the address is a global.
-define void @f9(i16 *%targetptr) {
+define dso_local void @f9(i16 *%targetptr) {
 ; CHECK-LABEL: f9:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
@@ -146,7 +146,7 @@ exit:
 
 ; Check that CRJ is used for checking order between two zero-extending
 ; byte loads, even if the original comparison was unsigned.
-define void @f10(i8 *%targetptr1) {
+define dso_local void @f10(i8 *%targetptr1) {
 ; CHECK-LABEL: f10:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
@@ -168,7 +168,7 @@ exit:
 }
 
 ; ...likewise halfword loads.
-define void @f11(i16 *%targetptr1) {
+define dso_local void @f11(i16 *%targetptr1) {
 ; CHECK-LABEL: f11:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
diff --git a/llvm/test/CodeGen/SystemZ/int-cmp-36.ll b/llvm/test/CodeGen/SystemZ/int-cmp-36.ll
index fc0e40e..eb1de72 100644
--- a/llvm/test/CodeGen/SystemZ/int-cmp-36.ll
+++ b/llvm/test/CodeGen/SystemZ/int-cmp-36.ll
@@ -3,11 +3,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
-@g = global i16 1
-@h = global i16 1, align 1, section "foo"
+@g = dso_local global i16 1
+@h = dso_local global i16 1, align 1, section "foo"
 
 ; Check signed comparison.
-define i32 @f1(i32 %src1) {
+define dso_local i32 @f1(i32 %src1) {
 ; CHECK-LABEL: f1:
 ; CHECK: chrl %r2, g
 ; CHECK-NEXT: blr %r14
@@ -26,7 +26,7 @@ exit:
 }
 
 ; Check unsigned comparison, which cannot use CHRL.
-define i32 @f2(i32 %src1) {
+define dso_local i32 @f2(i32 %src1) {
 ; CHECK-LABEL: f2:
 ; CHECK-NOT: chrl
 ; CHECK: br %r14
@@ -44,7 +44,7 @@ exit:
 }
 
 ; Check equality.
-define i32 @f3(i32 %src1) {
+define dso_local i32 @f3(i32 %src1) {
 ; CHECK-LABEL: f3:
 ; CHECK: chrl %r2, g
 ; CHECK-NEXT: ber %r14
@@ -63,7 +63,7 @@ exit:
 }
 
 ; Check inequality.
-define i32 @f4(i32 %src1) {
+define dso_local i32 @f4(i32 %src1) {
 ; CHECK-LABEL: f4:
 ; CHECK: chrl %r2, g
 ; CHECK-NEXT: blhr %r14
@@ -82,7 +82,7 @@ exit:
 }
 
 ; Repeat f1 with an unaligned address.
-define i32 @f5(i32 %src1) {
+define dso_local i32 @f5(i32 %src1) {
 ; CHECK-LABEL: f5:
 ; CHECK: lgrl [[REG:%r[0-5]]], h@GOT
 ; CHECK: ch %r2, 0([[REG]])
@@ -102,7 +102,7 @@ exit:
 }
 
 ; Check the comparison can be reversed if that allows CHRL to be used.
-define i32 @f6(i32 %src2) {
+define dso_local i32 @f6(i32 %src2) {
 ; CHECK-LABEL: f6:
 ; CHECK: chrl %r2, g
 ; CHECK-NEXT: bhr %r14
diff --git a/llvm/test/CodeGen/SystemZ/int-cmp-37.ll b/llvm/test/CodeGen/SystemZ/int-cmp-37.ll
index 28cabf7..3eb338c 100644
--- a/llvm/test/CodeGen/SystemZ/int-cmp-37.ll
+++ b/llvm/test/CodeGen/SystemZ/int-cmp-37.ll
@@ -3,11 +3,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
-@g = global i16 1
-@h = global i16 1, align 1, section "foo"
+@g = dso_local global i16 1
+@h = dso_local global i16 1, align 1, section "foo"
 
 ; Check unsigned comparison.
-define i32 @f1(i32 %src1) {
+define dso_local i32 @f1(i32 %src1) {
 ; CHECK-LABEL: f1:
 ; CHECK: clhrl %r2, g
 ; CHECK-NEXT: jl
@@ -27,7 +27,7 @@ exit:
 }
 
 ; Check signed comparison.
-define i32 @f2(i32 %src1) {
+define dso_local i32 @f2(i32 %src1) {
 ; CHECK-LABEL: f2:
 ; CHECK-NOT: clhrl
 ; CHECK: br %r14
@@ -46,7 +46,7 @@ exit:
 }
 
 ; Check equality.
-define i32 @f3(i32 %src1) {
+define dso_local i32 @f3(i32 %src1) {
 ; CHECK-LABEL: f3:
 ; CHECK: clhrl %r2, g
 ; CHECK-NEXT: je
@@ -66,7 +66,7 @@ exit:
 }
 
 ; Check inequality.
-define i32 @f4(i32 %src1) {
+define dso_local i32 @f4(i32 %src1) {
 ; CHECK-LABEL: f4:
 ; CHECK: clhrl %r2, g
 ; CHECK-NEXT: jlh
@@ -86,7 +86,7 @@ exit:
 }
 
 ; Repeat f1 with an unaligned address.
-define i32 @f5(i32 %src1) {
+define dso_local i32 @f5(i32 %src1) {
 ; CHECK-LABEL: f5:
 ; CHECK: lgrl [[REG:%r[0-5]]], h@GOT
 ; CHECK: llh [[VAL:%r[0-5]]], 0([[REG]])
@@ -107,7 +107,7 @@ exit:
 }
 
 ; Check the comparison can be reversed if that allows CLHRL to be used.
-define i32 @f6(i32 %src2) {
+define dso_local i32 @f6(i32 %src2) {
 ; CHECK-LABEL: f6:
 ; CHECK: clhrl %r2, g
 ; CHECK-NEXT: jh {{\.L.*}}
diff --git a/llvm/test/CodeGen/SystemZ/int-cmp-38.ll b/llvm/test/CodeGen/SystemZ/int-cmp-38.ll
index 5f67c7f..32ab73b 100644
--- a/llvm/test/CodeGen/SystemZ/int-cmp-38.ll
+++ b/llvm/test/CodeGen/SystemZ/int-cmp-38.ll
@@ -3,11 +3,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
-@g = global i32 1
-@h = global i32 1, align 2, section "foo"
+@g = dso_local global i32 1
+@h = dso_local global i32 1, align 2, section "foo"
 
 ; Check signed comparisons.
-define i32 @f1(i32 %src1) {
+define dso_local i32 @f1(i32 %src1) {
 ; CHECK-LABEL: f1:
 ; CHECK: crl %r2, g
 ; CHECK-NEXT: blr %r14
@@ -25,7 +25,7 @@ exit:
 }
 
 ; Check unsigned comparisons.
-define i32 @f2(i32 %src1) {
+define dso_local i32 @f2(i32 %src1) {
 ; CHECK-LABEL: f2:
 ; CHECK: clrl %r2, g
 ; CHECK-NEXT: blr %r14
@@ -43,7 +43,7 @@ exit:
 }
 
 ; Check equality, which can use CRL or CLRL.
-define i32 @f3(i32 %src1) {
+define dso_local i32 @f3(i32 %src1) {
 ; CHECK-LABEL: f3:
 ; CHECK: c{{l?}}rl %r2, g
 ; CHECK-NEXT: ber %r14
@@ -61,7 +61,7 @@ exit:
 }
 
 ; ...likewise inequality.
-define i32 @f4(i32 %src1) {
+define dso_local i32 @f4(i32 %src1) {
 ; CHECK-LABEL: f4:
 ; CHECK: c{{l?}}rl %r2, g
 ; CHECK-NEXT: blhr %r14
@@ -79,7 +79,7 @@ exit:
 }
 
 ; Repeat f1 with an unaligned address.
-define i32 @f5(i32 %src1) {
+define dso_local i32 @f5(i32 %src1) {
 ; CHECK-LABEL: f5:
 ; CHECK: larl [[REG:%r[0-5]]], h
 ; CHECK: c %r2, 0([[REG]])
@@ -98,7 +98,7 @@ exit:
 }
 
 ; Repeat f2 with an unaligned address.
-define i32 @f6(i32 %src1) {
+define dso_local i32 @f6(i32 %src1) {
 ; CHECK-LABEL: f6:
 ; CHECK: larl [[REG:%r[0-5]]], h
 ; CHECK: cl %r2, 0([[REG]])
@@ -117,7 +117,7 @@ exit:
 }
 
 ; Check the comparison can be reversed if that allows CRL to be used.
-define i32 @f7(i32 %src2) {
+define dso_local i32 @f7(i32 %src2) {
 ; CHECK-LABEL: f7:
 ; CHECK: crl %r2, g
 ; CHECK-NEXT: bhr %r14
diff --git a/llvm/test/CodeGen/SystemZ/int-cmp-39.ll b/llvm/test/CodeGen/SystemZ/int-cmp-39.ll
index 504aab8..c5f07e5 100644
--- a/llvm/test/CodeGen/SystemZ/int-cmp-39.ll
+++ b/llvm/test/CodeGen/SystemZ/int-cmp-39.ll
@@ -3,11 +3,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
-@g = global i16 1
-@h = global i16 1, align 1, section "foo"
+@g = dso_local global i16 1
+@h = dso_local global i16 1, align 1, section "foo"
 
 ; Check signed comparison.
-define i64 @f1(i64 %src1) {
+define dso_local i64 @f1(i64 %src1) {
 ; CHECK-LABEL: f1:
 ; CHECK: cghrl %r2, g
 ; CHECK-NEXT: blr %r14
@@ -26,7 +26,7 @@ exit:
 }
 
 ; Check unsigned comparison, which cannot use CHRL.
-define i64 @f2(i64 %src1) {
+define dso_local i64 @f2(i64 %src1) {
 ; CHECK-LABEL: f2:
 ; CHECK-NOT: cghrl
 ; CHECK: br %r14
@@ -44,7 +44,7 @@ exit:
 }
 
 ; Check equality.
-define i64 @f3(i64 %src1) {
+define dso_local i64 @f3(i64 %src1) {
 ; CHECK-LABEL: f3:
 ; CHECK: cghrl %r2, g
 ; CHECK-NEXT: ber %r14
@@ -63,7 +63,7 @@ exit:
 }
 
 ; Check inequality.
-define i64 @f4(i64 %src1) {
+define dso_local i64 @f4(i64 %src1) {
 ; CHECK-LABEL: f4:
 ; CHECK: cghrl %r2, g
 ; CHECK-NEXT: blhr %r14
@@ -82,7 +82,7 @@ exit:
 }
 
 ; Repeat f1 with an unaligned address.
-define i64 @f5(i64 %src1) {
+define dso_local i64 @f5(i64 %src1) {
 ; CHECK-LABEL: f5:
 ; CHECK: lgrl [[REG:%r[0-5]]], h@GOT
 ; CHECK: cgh %r2, 0([[REG]])
@@ -102,7 +102,7 @@ exit:
 }
 
 ; Check the comparison can be reversed if that allows CGHRL to be used.
-define i64 @f6(i64 %src2) {
+define dso_local i64 @f6(i64 %src2) {
 ; CHECK-LABEL: f6:
 ; CHECK: cghrl %r2, g
 ; CHECK-NEXT: bhr %r14
diff --git a/llvm/test/CodeGen/SystemZ/int-cmp-40.ll b/llvm/test/CodeGen/SystemZ/int-cmp-40.ll
index 09bf903..8851d4a 100644
--- a/llvm/test/CodeGen/SystemZ/int-cmp-40.ll
+++ b/llvm/test/CodeGen/SystemZ/int-cmp-40.ll
@@ -3,11 +3,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
-@g = global i16 1
-@h = global i16 1, align 1, section "foo"
+@g = dso_local global i16 1
+@h = dso_local global i16 1, align 1, section "foo"
 
 ; Check unsigned comparison.
-define i64 @f1(i64 %src1) {
+define dso_local i64 @f1(i64 %src1) {
 ; CHECK-LABEL: f1:
 ; CHECK: clghrl %r2, g
 ; CHECK-NEXT: jl
@@ -27,7 +27,7 @@ exit:
 }
 
 ; Check signed comparison.
-define i64 @f2(i64 %src1) {
+define dso_local i64 @f2(i64 %src1) {
 ; CHECK-LABEL: f2:
 ; CHECK-NOT: clghrl
 ; CHECK: br %r14
@@ -46,7 +46,7 @@ exit:
 }
 
 ; Check equality.
-define i64 @f3(i64 %src1) {
+define dso_local i64 @f3(i64 %src1) {
 ; CHECK-LABEL: f3:
 ; CHECK: clghrl %r2, g
 ; CHECK-NEXT: je
@@ -66,7 +66,7 @@ exit:
 }
 
 ; Check inequality.
-define i64 @f4(i64 %src1) {
+define dso_local i64 @f4(i64 %src1) {
 ; CHECK-LABEL: f4:
 ; CHECK: clghrl %r2, g
 ; CHECK-NEXT: jlh
@@ -86,7 +86,7 @@ exit:
 }
 
 ; Repeat f1 with an unaligned address.
-define i64 @f5(i64 %src1) {
+define dso_local i64 @f5(i64 %src1) {
 ; CHECK-LABEL: f5:
 ; CHECK: lgrl [[REG:%r[0-5]]], h@GOT
 ; CHECK: llgh [[VAL:%r[0-5]]], 0([[REG]])
@@ -107,7 +107,7 @@ exit:
 }
 
 ; Check the comparison can be reversed if that allows CLGHRL to be used.
-define i64 @f6(i64 %src2) {
+define dso_local i64 @f6(i64 %src2) {
 ; CHECK-LABEL: f6:
 ; CHECK: clghrl %r2, g
 ; CHECK-NEXT: jh {{\.L.*}}
diff --git a/llvm/test/CodeGen/SystemZ/int-cmp-41.ll b/llvm/test/CodeGen/SystemZ/int-cmp-41.ll
index d0201b5..8435140 100644
--- a/llvm/test/CodeGen/SystemZ/int-cmp-41.ll
+++ b/llvm/test/CodeGen/SystemZ/int-cmp-41.ll
@@ -3,11 +3,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
-@g = global i32 1
-@h = global i32 1, align 2, section "foo"
+@g = dso_local global i32 1
+@h = dso_local global i32 1, align 2, section "foo"
 
 ; Check signed comparison.
-define i64 @f1(i64 %src1) {
+define dso_local i64 @f1(i64 %src1) {
 ; CHECK-LABEL: f1:
 ; CHECK: cgfrl %r2, g
 ; CHECK-NEXT: blr %r14
@@ -26,7 +26,7 @@ exit:
 }
 
 ; Check unsigned comparison, which cannot use CHRL.
-define i64 @f2(i64 %src1) {
+define dso_local i64 @f2(i64 %src1) {
 ; CHECK-LABEL: f2:
 ; CHECK-NOT: cgfrl
 ; CHECK: br %r14
@@ -44,7 +44,7 @@ exit:
 }
 
 ; Check equality.
-define i64 @f3(i64 %src1) {
+define dso_local i64 @f3(i64 %src1) {
 ; CHECK-LABEL: f3:
 ; CHECK: cgfrl %r2, g
 ; CHECK-NEXT: ber %r14
@@ -63,7 +63,7 @@ exit:
 }
 
 ; Check inequality.
-define i64 @f4(i64 %src1) {
+define dso_local i64 @f4(i64 %src1) {
 ; CHECK-LABEL: f4:
 ; CHECK: cgfrl %r2, g
 ; CHECK-NEXT: blhr %r14
@@ -82,7 +82,7 @@ exit:
 }
 
 ; Repeat f1 with an unaligned address.
-define i64 @f5(i64 %src1) {
+define dso_local i64 @f5(i64 %src1) {
 ; CHECK-LABEL: f5:
 ; CHECK: larl [[REG:%r[0-5]]], h
 ; CHECK: cgf %r2, 0([[REG]])
@@ -102,7 +102,7 @@ exit:
 }
 
 ; Check the comparison can be reversed if that allows CGFRL to be used.
-define i64 @f6(i64 %src2) {
+define dso_local i64 @f6(i64 %src2) {
 ; CHECK-LABEL: f6:
 ; CHECK: cgfrl %r2, g
 ; CHECK-NEXT: bhr %r14
diff --git a/llvm/test/CodeGen/SystemZ/int-cmp-42.ll b/llvm/test/CodeGen/SystemZ/int-cmp-42.ll
index 02fa547..7e0533d4 100644
--- a/llvm/test/CodeGen/SystemZ/int-cmp-42.ll
+++ b/llvm/test/CodeGen/SystemZ/int-cmp-42.ll
@@ -3,11 +3,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
-@g = global i32 1
-@h = global i32 1, align 2, section "foo"
+@g = dso_local global i32 1
+@h = dso_local global i32 1, align 2, section "foo"
 
 ; Check unsigned comparison.
-define i64 @f1(i64 %src1) {
+define dso_local i64 @f1(i64 %src1) {
 ; CHECK-LABEL: f1:
 ; CHECK: clgfrl %r2, g
 ; CHECK-NEXT: blr %r14
@@ -26,7 +26,7 @@ exit:
 }
 
 ; Check signed comparison.
-define i64 @f2(i64 %src1) {
+define dso_local i64 @f2(i64 %src1) {
 ; CHECK-LABEL: f2:
 ; CHECK-NOT: clgfrl
 ; CHECK: br %r14
@@ -44,7 +44,7 @@ exit:
 }
 
 ; Check equality.
-define i64 @f3(i64 %src1) {
+define dso_local i64 @f3(i64 %src1) {
 ; CHECK-LABEL: f3:
 ; CHECK: clgfrl %r2, g
 ; CHECK-NEXT: ber %r14
@@ -63,7 +63,7 @@ exit:
 }
 
 ; Check inequality.
-define i64 @f4(i64 %src1) {
+define dso_local i64 @f4(i64 %src1) {
 ; CHECK-LABEL: f4:
 ; CHECK: clgfrl %r2, g
 ; CHECK-NEXT: blhr %r14
@@ -82,7 +82,7 @@ exit:
 }
 
 ; Repeat f1 with an unaligned address.
-define i64 @f5(i64 %src1) {
+define dso_local i64 @f5(i64 %src1) {
 ; CHECK-LABEL: f5:
 ; CHECK: larl [[REG:%r[0-5]]], h
 ; CHECK: clgf %r2, 0([[REG]])
@@ -102,7 +102,7 @@ exit:
 }
 
 ; Check the comparison can be reversed if that allows CLGFRL to be used.
-define i64 @f6(i64 %src2) {
+define dso_local i64 @f6(i64 %src2) {
 ; CHECK-LABEL: f6:
 ; CHECK: clgfrl %r2, g
 ; CHECK-NEXT: bhr %r14
diff --git a/llvm/test/CodeGen/SystemZ/int-cmp-43.ll b/llvm/test/CodeGen/SystemZ/int-cmp-43.ll
index cdeb47d..cab58ae 100644
--- a/llvm/test/CodeGen/SystemZ/int-cmp-43.ll
+++ b/llvm/test/CodeGen/SystemZ/int-cmp-43.ll
@@ -3,11 +3,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
-@g = global i64 1
-@h = global i64 1, align 4, section "foo"
+@g = dso_local global i64 1
+@h = dso_local global i64 1, align 4, section "foo"
 
 ; Check signed comparisons.
-define i64 @f1(i64 %src1) {
+define dso_local i64 @f1(i64 %src1) {
 ; CHECK-LABEL: f1:
 ; CHECK: cgrl %r2, g
 ; CHECK-NEXT: blr %r14
@@ -25,7 +25,7 @@ exit:
 }
 
 ; Check unsigned comparisons.
-define i64 @f2(i64 %src1) {
+define dso_local i64 @f2(i64 %src1) {
 ; CHECK-LABEL: f2:
 ; CHECK: clgrl %r2, g
 ; CHECK-NEXT: blr %r14
@@ -43,7 +43,7 @@ exit:
 }
 
 ; Check equality, which can use CRL or CLRL.
-define i64 @f3(i64 %src1) {
+define dso_local i64 @f3(i64 %src1) {
 ; CHECK-LABEL: f3:
 ; CHECK: c{{l?}}grl %r2, g
 ; CHECK-NEXT: ber %r14
@@ -61,7 +61,7 @@ exit:
 }
 
 ; ...likewise inequality.
-define i64 @f4(i64 %src1) {
+define dso_local i64 @f4(i64 %src1) {
 ; CHECK-LABEL: f4:
 ; CHECK: c{{l?}}grl %r2, g
 ; CHECK-NEXT: blhr %r14
@@ -79,7 +79,7 @@ exit:
 }
 
 ; Repeat f1 with an unaligned address.
-define i64 @f5(i64 %src1) {
+define dso_local i64 @f5(i64 %src1) {
 ; CHECK-LABEL: f5:
 ; CHECK: larl [[REG:%r[0-5]]], h
 ; CHECK: cg %r2, 0([[REG]])
@@ -98,7 +98,7 @@ exit:
 }
 
 ; Check the comparison can be reversed if that allows CGRL to be used.
-define i64 @f6(i64 %src2) {
+define dso_local i64 @f6(i64 %src2) {
 ; CHECK-LABEL: f6:
 ; CHECK: cgrl %r2, g
 ; CHECK-NEXT: bhr %r14
diff --git a/llvm/test/CodeGen/SystemZ/int-move-08.ll b/llvm/test/CodeGen/SystemZ/int-move-08.ll
index 75d5aed..67edbb8 100644
--- a/llvm/test/CodeGen/SystemZ/int-move-08.ll
+++ b/llvm/test/CodeGen/SystemZ/int-move-08.ll
@@ -2,19 +2,19 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
-@gsrc16 = global i16 1
-@gsrc32 = global i32 1
-@gdst16 = global i16 2
-@gdst32 = global i32 2
-@gsrc16u = global i16 1, align 1, section "foo"
-@gsrc32u = global i32 1, align 2, section "foo"
-@gdst16u = global i16 2, align 1, section "foo"
-@gdst32u = global i32 2, align 2, section "foo"
-@garray8 = global [2 x i8] [i8 100, i8 101]
-@garray16 = global [2 x i16] [i16 102, i16 103]
+@gsrc16 = dso_local global i16 1
+@gsrc32 = dso_local global i32 1
+@gdst16 = dso_local global i16 2
+@gdst32 = dso_local global i32 2
+@gsrc16u = dso_local global i16 1, align 1, section "foo"
+@gsrc32u = dso_local global i32 1, align 2, section "foo"
+@gdst16u = dso_local global i16 2, align 1, section "foo"
+@gdst32u = dso_local global i32 2, align 2, section "foo"
+@garray8 = dso_local global [2 x i8] [i8 100, i8 101]
+@garray16 = dso_local global [2 x i16] [i16 102, i16 103]
 
 ; Check sign-extending loads from i16.
-define i32 @f1() {
+define dso_local i32 @f1() {
 ; CHECK-LABEL: f1:
 ; CHECK: lhrl %r2, gsrc16
 ; CHECK: br %r14
@@ -24,7 +24,7 @@ define i32 @f1() {
 }
 
 ; Check zero-extending loads from i16.
-define i32 @f2() {
+define dso_local i32 @f2() {
 ; CHECK-LABEL: f2:
 ; CHECK: llhrl %r2, gsrc16
 ; CHECK: br %r14
@@ -34,7 +34,7 @@ define i32 @f2() {
 }
 
 ; Check truncating 16-bit stores.
-define void @f3(i32 %val) {
+define dso_local void @f3(i32 %val) {
 ; CHECK-LABEL: f3:
 ; CHECK: sthrl %r2, gdst16
 ; CHECK: br %r14
@@ -44,7 +44,7 @@ define void @f3(i32 %val) {
 }
 
 ; Check plain loads and stores.
-define void @f4() {
+define dso_local void @f4() {
 ; CHECK-LABEL: f4:
 ; CHECK: lrl %r0, gsrc32
 ; CHECK: strl %r0, gdst32
@@ -55,7 +55,7 @@ define void @f4() {
 }
 
 ; Repeat f1 with an unaligned variable.
-define i32 @f5() {
+define dso_local i32 @f5() {
 ; CHECK-LABEL: f5:
 ; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u
 ; CHECK: lh %r2, 0([[REG]])
@@ -66,7 +66,7 @@ define i32 @f5() {
 }
 
 ; Repeat f2 with an unaligned variable.
-define i32 @f6() {
+define dso_local i32 @f6() {
 ; CHECK-LABEL: f6:
 ; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u
 ; CHECK: llh %r2, 0([[REG]])
@@ -77,7 +77,7 @@ define i32 @f6() {
 }
 
 ; Repeat f3 with an unaligned variable.
-define void @f7(i32 %val) {
+define dso_local void @f7(i32 %val) {
 ; CHECK-LABEL: f7:
 ; CHECK: lgrl [[REG:%r[0-5]]], gdst16u
 ; CHECK: sth %r2, 0([[REG]])
@@ -88,7 +88,7 @@ define void @f7(i32 %val) {
 }
 
 ; Repeat f4 with unaligned variables.
-define void @f8() {
+define dso_local void @f8() {
 ; CHECK-LABEL: f8:
 ; CHECK: larl [[REG:%r[0-5]]], gsrc32u
 ; CHECK: l [[VAL:%r[0-5]]], 0([[REG]])
@@ -102,7 +102,7 @@ define void @f8() {
 
 ; Test a case where we want to use one LARL for accesses to two different
 ; parts of a variable.
-define void @f9() {
+define dso_local void @f9() {
 ; CHECK-LABEL: f9:
 ; CHECK: larl [[REG:%r[0-5]]], garray8
 ; CHECK: llc [[VAL:%r[0-5]]], 0([[REG]])
@@ -119,7 +119,7 @@ define void @f9() {
 
 ; Test a case where we want to use separate relative-long addresses for
 ; two different parts of a variable.
-define void @f10() {
+define dso_local void @f10() {
 ; CHECK-LABEL: f10:
 ; CHECK: llhrl [[VAL:%r[0-5]]], garray16
 ; CHECK: srl [[VAL]], 1
diff --git a/llvm/test/CodeGen/SystemZ/int-move-09.ll b/llvm/test/CodeGen/SystemZ/int-move-09.ll
index 0a039e9..023365f 100644
--- a/llvm/test/CodeGen/SystemZ/int-move-09.ll
+++ b/llvm/test/CodeGen/SystemZ/int-move-09.ll
@@ -2,21 +2,21 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
-@gsrc16 = global i16 1
-@gsrc32 = global i32 1
-@gsrc64 = global i64 1
-@gdst16 = global i16 2
-@gdst32 = global i32 2
-@gdst64 = global i64 2
-@gsrc16u = global i16 1, align 1, section "foo"
-@gsrc32u = global i32 1, align 2, section "foo"
-@gsrc64u = global i64 1, align 4, section "foo"
-@gdst16u = global i16 2, align 1, section "foo"
-@gdst32u = global i32 2, align 2, section "foo"
-@gdst64u = global i64 2, align 4, section "foo"
+@gsrc16 = dso_local global i16 1
+@gsrc32 = dso_local global i32 1
+@gsrc64 = dso_local global i64 1
+@gdst16 = dso_local global i16 2
+@gdst32 = dso_local global i32 2
+@gdst64 = dso_local global i64 2
+@gsrc16u = dso_local global i16 1, align 1, section "foo"
+@gsrc32u = dso_local global i32 1, align 2, section "foo"
+@gsrc64u = dso_local global i64 1, align 4, section "foo"
+@gdst16u = dso_local global i16 2, align 1, section "foo"
+@gdst32u = dso_local global i32 2, align 2, section "foo"
+@gdst64u = dso_local global i64 2, align 4, section "foo"
 
 ; Check sign-extending loads from i16.
-define i64 @f1() {
+define dso_local i64 @f1() {
 ; CHECK-LABEL: f1:
 ; CHECK: lghrl %r2, gsrc16
 ; CHECK: br %r14
@@ -26,7 +26,7 @@ define i64 @f1() {
 }
 
 ; Check zero-extending loads from i16.
-define i64 @f2() {
+define dso_local i64 @f2() {
 ; CHECK-LABEL: f2:
 ; CHECK: llghrl %r2, gsrc16
 ; CHECK: br %r14
@@ -36,7 +36,7 @@ define i64 @f2() {
 }
 
 ; Check sign-extending loads from i32.
-define i64 @f3() {
+define dso_local i64 @f3() {
 ; CHECK-LABEL: f3:
 ; CHECK: lgfrl %r2, gsrc32
 ; CHECK: br %r14
@@ -46,7 +46,7 @@ define i64 @f3() {
 }
 
 ; Check zero-extending loads from i32.
-define i64 @f4() {
+define dso_local i64 @f4() {
 ; CHECK-LABEL: f4:
 ; CHECK: llgfrl %r2, gsrc32
 ; CHECK: br %r14
@@ -56,7 +56,7 @@ define i64 @f4() {
 }
 
 ; Check truncating 16-bit stores.
-define void @f5(i64 %val) {
+define dso_local void @f5(i64 %val) {
 ; CHECK-LABEL: f5:
 ; CHECK: sthrl %r2, gdst16
 ; CHECK: br %r14
@@ -66,7 +66,7 @@ define void @f5(i64 %val) {
 }
 
 ; Check truncating 32-bit stores.
-define void @f6(i64 %val) {
+define dso_local void @f6(i64 %val) {
 ; CHECK-LABEL: f6:
 ; CHECK: strl %r2, gdst32
 ; CHECK: br %r14
@@ -76,7 +76,7 @@ define void @f6(i64 %val) {
 }
 
 ; Check plain loads and stores.
-define void @f7() {
+define dso_local void @f7() {
 ; CHECK-LABEL: f7:
 ; CHECK: lgrl %r0, gsrc64
 ; CHECK: stgrl %r0, gdst64
@@ -87,7 +87,7 @@ define void @f7() {
 }
 
 ; Repeat f1 with an unaligned variable.
-define i64 @f8() {
+define dso_local i64 @f8() {
 ; CHECK-LABEL: f8:
 ; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u@GOT
 ; CHECK: lgh %r2, 0([[REG]])
@@ -98,7 +98,7 @@ define i64 @f8() {
 }
 
 ; Repeat f2 with an unaligned variable.
-define i64 @f9() {
+define dso_local i64 @f9() {
 ; CHECK-LABEL: f9:
 ; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u@GOT
 ; CHECK: llgh %r2, 0([[REG]])
@@ -109,7 +109,7 @@ define i64 @f9() {
 }
 
 ; Repeat f3 with an unaligned variable.
-define i64 @f10() {
+define dso_local i64 @f10() {
 ; CHECK-LABEL: f10:
 ; CHECK: larl [[REG:%r[0-5]]], gsrc32u
 ; CHECK: lgf %r2, 0([[REG]])
@@ -120,7 +120,7 @@ define i64 @f10() {
 }
 
 ; Repeat f4 with an unaligned variable.
-define i64 @f11() {
+define dso_local i64 @f11() {
 ; CHECK-LABEL: f11:
 ; CHECK: larl [[REG:%r[0-5]]], gsrc32u
 ; CHECK: llgf %r2, 0([[REG]])
@@ -131,7 +131,7 @@ define i64 @f11() {
 }
 
 ; Repeat f5 with an unaligned variable.
-define void @f12(i64 %val) {
+define dso_local void @f12(i64 %val) {
 ; CHECK-LABEL: f12:
 ; CHECK: lgrl [[REG:%r[0-5]]], gdst16u@GOT
 ; CHECK: sth %r2, 0([[REG]])
@@ -142,7 +142,7 @@ define void @f12(i64 %val) {
 }
 
 ; Repeat f6 with an unaligned variable.
-define void @f13(i64 %val) {
+define dso_local void @f13(i64 %val) {
 ; CHECK-LABEL: f13:
 ; CHECK: larl [[REG:%r[0-5]]], gdst32u
 ; CHECK: st %r2, 0([[REG]])
@@ -153,7 +153,7 @@ define void @f13(i64 %val) {
 }
 
 ; Repeat f7 with unaligned variables.
-define void @f14() {
+define dso_local void @f14() {
 ; CHECK-LABEL: f14:
 ; CHECK: larl [[REG:%r[0-5]]], gsrc64u
 ; CHECK: lg [[VAL:%r[0-5]]], 0([[REG]])
diff --git a/llvm/test/CodeGen/SystemZ/int-move-10.ll b/llvm/test/CodeGen/SystemZ/int-move-10.ll
index 8b8b9ed..190c307 100644
--- a/llvm/test/CodeGen/SystemZ/int-move-10.ll
+++ b/llvm/test/CodeGen/SystemZ/int-move-10.ll
@@ -22,17 +22,17 @@
 %packed.i16i64 = type <{ i16, i64 }>
 %packed.i8i16 = type <{ i8, i16 }>
 
-@A_align2 = global %packed.i16i32 zeroinitializer, align 2
-@B_align2 = global %packed.i16i32i16i32 zeroinitializer, align 2
-@C_align2 = global %packed.i16i64 zeroinitializer, align 2
-@D_align4 = global %packed.i16i32 zeroinitializer, align 4
-@E_align4 = global %packed.i16i32i16i32 zeroinitializer, align 4
-@F_align2 = global %packed.i8i16 zeroinitializer, align 2
+@A_align2 = dso_local global %packed.i16i32 zeroinitializer, align 2
+@B_align2 = dso_local global %packed.i16i32i16i32 zeroinitializer, align 2
+@C_align2 = dso_local global %packed.i16i64 zeroinitializer, align 2
+@D_align4 = dso_local global %packed.i16i32 zeroinitializer, align 4
+@E_align4 = dso_local global %packed.i16i32i16i32 zeroinitializer, align 4
+@F_align2 = dso_local global %packed.i8i16 zeroinitializer, align 2
 
 ;;; Stores
 
 ; unaligned packed struct + 2  -> unaligned address
-define void @f1() {
+define dso_local void @f1() {
 ; CHECK-LABEL: f1:
 ; CHECK: larl %r1, A_align2
 ; CHECK: mvhi 2(%r1), 0
@@ -42,7 +42,7 @@ define void @f1() {
 }
 
 ; unaligned packed struct  + 8  -> unaligned address
-define void @f2() {
+define dso_local void @f2() {
 ; CHECK-LABEL: f2:
 ; CHECK: larl %r1, B_align2
 ; CHECK: mvhi 8(%r1), 0
@@ -52,7 +52,7 @@ define void @f2() {
 }
 
 ; aligned packed struct + 2  -> unaligned address
-define void @f3() {
+define dso_local void @f3() {
 ; CHECK-LABEL: f3:
 ; CHECK: larl %r1, D_align4
 ; CHECK: mvhi 2(%r1), 0
@@ -62,7 +62,7 @@ define void @f3() {
 }
 
 ; aligned packed struct + 8  -> aligned address
-define void @f4() {
+define dso_local void @f4() {
 ; CHECK-LABEL: f4:
 ; CHECK: lhi %r0, 0
 ; CHECK: strl %r0, E_align4+8
@@ -71,7 +71,7 @@ define void @f4() {
   ret void
 }
 
-define void @f5() {
+define dso_local void @f5() {
 ; CHECK-LABEL: f5:
 ; CHECK: larl %r1, C_align2
 ; CHECK: mvghi 2(%r1), 0
@@ -80,14 +80,14 @@ define void @f5() {
   ret void
 }
 
-define void @f6() {
+define dso_local void @f6() {
 ; CHECK-LABEL: f6:
 ; CHECK-NOT: sthrl
   store i16 0, i16* getelementptr inbounds (%packed.i8i16, %packed.i8i16* @F_align2, i64 0, i32 1), align 2
   ret void
 }
 
-define void @f7(i64* %Src) {
+define dso_local void @f7(i64* %Src) {
 ; CHECK-LABEL: f7:
 ; CHECK: lg %r0, 0(%r2)
 ; CHECK: larl %r1, D_align4
@@ -99,7 +99,7 @@ define void @f7(i64* %Src) {
   ret void
 }
 
-define void @f8(i64* %Src) {
+define dso_local void @f8(i64* %Src) {
 ; CHECK-LABEL: f8:
 ; CHECK-NOT: sthrl
   %L = load i64, i64* %Src
@@ -111,7 +111,7 @@ define void @f8(i64* %Src) {
 ;;; Loads
 
 ; unaligned packed struct + 2  -> unaligned address
-define i32 @f9() {
+define dso_local i32 @f9() {
 ; CHECK-LABEL: f9:
 ; CHECK: larl %r1, A_align2
 ; CHECK: l %r2, 2(%r1)
@@ -121,7 +121,7 @@ define i32 @f9() {
 }
 
 ; unaligned packed struct  + 8  -> unaligned address
-define i32 @f10() {
+define dso_local i32 @f10() {
 ; CHECK-LABEL: f10:
 ; CHECK: larl %r1, B_align2
 ; CHECK: l %r2, 8(%r1)
@@ -131,7 +131,7 @@ define i32 @f10() {
 }
 
 ; aligned packed struct + 2  -> unaligned address
-define i32 @f11() {
+define dso_local i32 @f11() {
 ; CHECK-LABEL: f11:
 ; CHECK: larl %r1, D_align4
 ; CHECK: l %r2, 2(%r1)
@@ -141,7 +141,7 @@ define i32 @f11() {
 }
 
 ; aligned packed struct + 8  -> aligned address
-define i32 @f12() {
+define dso_local i32 @f12() {
 ; CHECK-LABEL: f12:
 ; CHECK: lrl %r2, E_align4+8
 ; CHECK: br %r14
@@ -149,7 +149,7 @@ define i32 @f12() {
   ret i32 %L
 }
 
-define i64 @f13() {
+define dso_local i64 @f13() {
 ; CHECK-LABEL: f13:
 ; CHECK: larl %r1, C_align2
 ; CHECK: lg %r2, 2(%r1)
@@ -158,7 +158,7 @@ define i64 @f13() {
   ret i64 %L
 }
 
-define i32 @f14() {
+define dso_local i32 @f14() {
 ; CHECK-LABEL: f14:
 ; CHECK-NOT: lhrl
   %L = load i16, i16* getelementptr inbounds (%packed.i8i16, %packed.i8i16* @F_align2, i64 0, i32 1), align 2
@@ -166,7 +166,7 @@ define i32 @f14() {
   ret i32 %ext
 }
 
-define i64 @f15() {
+define dso_local i64 @f15() {
 ; CHECK-LABEL: f15:
 ; CHECK-NOT: llghrl
   %L = load i16, i16* getelementptr inbounds (%packed.i8i16, %packed.i8i16* @F_align2, i64 0, i32 1), align 2
@@ -176,7 +176,7 @@ define i64 @f15() {
 
 ;;; Loads folded into compare instructions
 
-define i32 @f16(i32 %src1) {
+define dso_local i32 @f16(i32 %src1) {
 ; CHECK-LABEL: f16:
 ; CHECK: larl %r1, A_align2
 ; CHECK: c %r2, 2(%r1)
@@ -192,7 +192,7 @@ exit:
   ret i32 %res
 }
 
-define i64 @f17(i64 %src1) {
+define dso_local i64 @f17(i64 %src1) {
 ; CHECK-LABEL: f17:
 ; CHECK: larl %r1, C_align2
 ; CHECK: clg %r2, 2(%r1)
diff --git a/llvm/test/CodeGen/SystemZ/la-01.ll b/llvm/test/CodeGen/SystemZ/la-01.ll
index bbe1c9d..7eda8a9 100644
--- a/llvm/test/CodeGen/SystemZ/la-01.ll
+++ b/llvm/test/CodeGen/SystemZ/la-01.ll
@@ -4,21 +4,21 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 @e4 = external dso_local global i32
-@d4 = global i32 1
+@d4 = dso_local global i32 1
 @e2 = external dso_local global i32, align 2
-@d2 = global i32 1, align 2
+@d2 = dso_local global i32 1, align 2
 @e1 = external dso_local global i32, align 1
-@d1 = global i32 1, align 1
+@d1 = dso_local global i32 1, align 1
 
 declare dso_local void @ef()
-define void @df() {
+define dso_local void @df() {
   ret void
 }
 
 declare dso_local void @foo(i32 *)
 
 ; Test a load of a fully-aligned external variable.
-define i32 *@f1() {
+define dso_local i32 *@f1() {
 ; CHECK-LABEL: f1:
 ; CHECK: larl %r2, e4
 ; CHECK-NEXT: br %r14
@@ -26,7 +26,7 @@ define i32 *@f1() {
 }
 
 ; Test a load of a fully-aligned local variable.
-define i32 *@f2() {
+define dso_local i32 *@f2() {
 ; CHECK-LABEL: f2:
 ; CHECK: larl %r2, d4
 ; CHECK-NEXT: br %r14
@@ -34,7 +34,7 @@ define i32 *@f2() {
 }
 
 ; Test a load of a 2-byte-aligned external variable.
-define i32 *@f3() {
+define dso_local i32 *@f3() {
 ; CHECK-LABEL: f3:
 ; CHECK: larl %r2, e2
 ; CHECK-NEXT: br %r14
@@ -42,7 +42,7 @@ define i32 *@f3() {
 }
 
 ; Test a load of a 2-byte-aligned local variable.
-define i32 *@f4() {
+define dso_local i32 *@f4() {
 ; CHECK-LABEL: f4:
 ; CHECK: larl %r2, d2
 ; CHECK-NEXT: br %r14
@@ -50,7 +50,7 @@ define i32 *@f4() {
 }
 
 ; Test a load of an unaligned external variable, which must go via the GOT.
-define i32 *@f5() {
+define dso_local i32 *@f5() {
 ; CHECK-LABEL: f5:
 ; CHECK: lgrl %r2, e1@GOT
 ; CHECK-NEXT: br %r14
@@ -58,7 +58,7 @@ define i32 *@f5() {
 }
 
 ; Test a load of an unaligned local variable, which must go via the GOT.
-define i32 *@f6() {
+define dso_local i32 *@f6() {
 ; CHECK-LABEL: f6:
 ; CHECK: lgrl %r2, d1@GOT
 ; CHECK-NEXT: br %r14
@@ -66,7 +66,7 @@ define i32 *@f6() {
 }
 
 ; Test a load of an external function.
-define void() *@f7() {
+define dso_local void() *@f7() {
 ; CHECK-LABEL: f7:
 ; CHECK: larl %r2, ef
 ; CHECK-NEXT: br %r14
@@ -74,7 +74,7 @@ define void() *@f7() {
 }
 
 ; Test a load of a local function.
-define void() *@f8() {
+define dso_local void() *@f8() {
 ; CHECK-LABEL: f8:
 ; CHECK: larl %r2, df
 ; CHECK-NEXT: br %r14
@@ -82,7 +82,7 @@ define void() *@f8() {
 }
 
 ; Test that LARL can be rematerialized.
-define i32 @f9() {
+define dso_local i32 @f9() {
 ; CHECK-LABEL: f9:
 ; CHECK: larl %r2, d2
 ; CHECK: brasl %r14, foo@PLT
diff --git a/llvm/test/CodeGen/SystemZ/memcpy-02.ll b/llvm/test/CodeGen/SystemZ/memcpy-02.ll
index f86ad50..a49e43b 100644
--- a/llvm/test/CodeGen/SystemZ/memcpy-02.ll
+++ b/llvm/test/CodeGen/SystemZ/memcpy-02.ll
@@ -2,17 +2,17 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
-@g1src = global i8 1
-@g1dst = global i8 1
-@g2src = global i16 2
-@g2dst = global i16 2
-@g3 = global i32 3
-@g4 = global i64 4
+@g1src = dso_local global i8 1
+@g1dst = dso_local global i8 1
+@g2src = dso_local global i16 2
+@g2dst = dso_local global i16 2
+@g3 = dso_local global i32 3
+@g4 = dso_local global i64 4
 @g5src = external dso_local global fp128, align 16
 @g5dst = external dso_local global fp128, align 16
 
 ; Test the simple i8 case.
-define void @f1(i8 *%ptr1) {
+define dso_local void @f1(i8 *%ptr1) {
 ; CHECK-LABEL: f1:
 ; CHECK: mvc 1(1,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -23,7 +23,7 @@ define void @f1(i8 *%ptr1) {
 }
 
 ; Test i8 cases where the value is zero-extended to 32 bits.
-define void @f2(i8 *%ptr1) {
+define dso_local void @f2(i8 *%ptr1) {
 ; CHECK-LABEL: f2:
 ; CHECK: mvc 1(1,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -36,7 +36,7 @@ define void @f2(i8 *%ptr1) {
 }
 
 ; Test i8 cases where the value is zero-extended to 64 bits.
-define void @f3(i8 *%ptr1) {
+define dso_local void @f3(i8 *%ptr1) {
 ; CHECK-LABEL: f3:
 ; CHECK: mvc 1(1,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -49,7 +49,7 @@ define void @f3(i8 *%ptr1) {
 }
 
 ; Test i8 cases where the value is sign-extended to 32 bits.
-define void @f4(i8 *%ptr1) {
+define dso_local void @f4(i8 *%ptr1) {
 ; CHECK-LABEL: f4:
 ; CHECK: mvc 1(1,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -62,7 +62,7 @@ define void @f4(i8 *%ptr1) {
 }
 
 ; Test i8 cases where the value is sign-extended to 64 bits.
-define void @f5(i8 *%ptr1) {
+define dso_local void @f5(i8 *%ptr1) {
 ; CHECK-LABEL: f5:
 ; CHECK: mvc 1(1,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -75,7 +75,7 @@ define void @f5(i8 *%ptr1) {
 }
 
 ; Test the simple i16 case.
-define void @f6(i16 *%ptr1) {
+define dso_local void @f6(i16 *%ptr1) {
 ; CHECK-LABEL: f6:
 ; CHECK: mvc 2(2,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -86,7 +86,7 @@ define void @f6(i16 *%ptr1) {
 }
 
 ; Test i16 cases where the value is zero-extended to 32 bits.
-define void @f7(i16 *%ptr1) {
+define dso_local void @f7(i16 *%ptr1) {
 ; CHECK-LABEL: f7:
 ; CHECK: mvc 2(2,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -99,7 +99,7 @@ define void @f7(i16 *%ptr1) {
 }
 
 ; Test i16 cases where the value is zero-extended to 64 bits.
-define void @f8(i16 *%ptr1) {
+define dso_local void @f8(i16 *%ptr1) {
 ; CHECK-LABEL: f8:
 ; CHECK: mvc 2(2,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -112,7 +112,7 @@ define void @f8(i16 *%ptr1) {
 }
 
 ; Test i16 cases where the value is sign-extended to 32 bits.
-define void @f9(i16 *%ptr1) {
+define dso_local void @f9(i16 *%ptr1) {
 ; CHECK-LABEL: f9:
 ; CHECK: mvc 2(2,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -125,7 +125,7 @@ define void @f9(i16 *%ptr1) {
 }
 
 ; Test i16 cases where the value is sign-extended to 64 bits.
-define void @f10(i16 *%ptr1) {
+define dso_local void @f10(i16 *%ptr1) {
 ; CHECK-LABEL: f10:
 ; CHECK: mvc 2(2,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -138,7 +138,7 @@ define void @f10(i16 *%ptr1) {
 }
 
 ; Test the simple i32 case.
-define void @f11(i32 *%ptr1) {
+define dso_local void @f11(i32 *%ptr1) {
 ; CHECK-LABEL: f11:
 ; CHECK: mvc 4(4,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -149,7 +149,7 @@ define void @f11(i32 *%ptr1) {
 }
 
 ; Test i32 cases where the value is zero-extended to 64 bits.
-define void @f12(i32 *%ptr1) {
+define dso_local void @f12(i32 *%ptr1) {
 ; CHECK-LABEL: f12:
 ; CHECK: mvc 4(4,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -162,7 +162,7 @@ define void @f12(i32 *%ptr1) {
 }
 
 ; Test i32 cases where the value is sign-extended to 64 bits.
-define void @f13(i32 *%ptr1) {
+define dso_local void @f13(i32 *%ptr1) {
 ; CHECK-LABEL: f13:
 ; CHECK: mvc 4(4,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -175,7 +175,7 @@ define void @f13(i32 *%ptr1) {
 }
 
 ; Test the i64 case.
-define void @f14(i64 *%ptr1) {
+define dso_local void @f14(i64 *%ptr1) {
 ; CHECK-LABEL: f14:
 ; CHECK: mvc 8(8,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -186,7 +186,7 @@ define void @f14(i64 *%ptr1) {
 }
 
 ; Test the f32 case.
-define void @f15(float *%ptr1) {
+define dso_local void @f15(float *%ptr1) {
 ; CHECK-LABEL: f15:
 ; CHECK: mvc 4(4,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -197,7 +197,7 @@ define void @f15(float *%ptr1) {
 }
 
 ; Test the f64 case.
-define void @f16(double *%ptr1) {
+define dso_local void @f16(double *%ptr1) {
 ; CHECK-LABEL: f16:
 ; CHECK: mvc 8(8,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -208,7 +208,7 @@ define void @f16(double *%ptr1) {
 }
 
 ; Test the f128 case.
-define void @f17(fp128 *%ptr1) {
+define dso_local void @f17(fp128 *%ptr1) {
 ; CHECK-LABEL: f17:
 ; CHECK: mvc 16(16,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -219,7 +219,7 @@ define void @f17(fp128 *%ptr1) {
 }
 
 ; Make sure that we don't use MVC if the load is volatile.
-define void @f18(i64 *%ptr1) {
+define dso_local void @f18(i64 *%ptr1) {
 ; CHECK-LABEL: f18:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
@@ -230,7 +230,7 @@ define void @f18(i64 *%ptr1) {
 }
 
 ; ...likewise the store.
-define void @f19(i64 *%ptr1) {
+define dso_local void @f19(i64 *%ptr1) {
 ; CHECK-LABEL: f19:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
@@ -243,7 +243,7 @@ define void @f19(i64 *%ptr1) {
 ; Test that MVC is not used for aligned loads and stores if there is
 ; no way of telling whether they alias.  We don't want to use MVC in
 ; cases where the addresses could be equal.
-define void @f20(i64 *%ptr1, i64 *%ptr2) {
+define dso_local void @f20(i64 *%ptr1, i64 *%ptr2) {
 ; CHECK-LABEL: f20:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
@@ -253,7 +253,7 @@ define void @f20(i64 *%ptr1, i64 *%ptr2) {
 }
 
 ; ...and again for unaligned loads and stores.
-define void @f21(i64 *%ptr1, i64 *%ptr2) {
+define dso_local void @f21(i64 *%ptr1, i64 *%ptr2) {
 ; CHECK-LABEL: f21:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
@@ -263,7 +263,7 @@ define void @f21(i64 *%ptr1, i64 *%ptr2) {
 }
 
 ; Test a case where there is definite overlap.
-define void @f22(i64 %base) {
+define dso_local void @f22(i64 %base) {
 ; CHECK-LABEL: f22:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
@@ -276,7 +276,7 @@ define void @f22(i64 %base) {
 }
 
 ; Test that we can use MVC for global addresses for i8.
-define void @f23(i8 *%ptr) {
+define dso_local void @f23(i8 *%ptr) {
 ; CHECK-LABEL: f23:
 ; CHECK-DAG: larl [[SRC:%r[0-5]]], g1src
 ; CHECK-DAG: larl [[DST:%r[0-5]]], g1dst
@@ -288,7 +288,7 @@ define void @f23(i8 *%ptr) {
 }
 
 ; Test that we use LHRL and STHRL for i16.
-define void @f24(i16 *%ptr) {
+define dso_local void @f24(i16 *%ptr) {
 ; CHECK-LABEL: f24:
 ; CHECK: lhrl [[REG:%r[0-5]]], g2src
 ; CHECK: sthrl [[REG]], g2dst
@@ -299,7 +299,7 @@ define void @f24(i16 *%ptr) {
 }
 
 ; Test that we use LRL for i32.
-define void @f25(i32 *%ptr) {
+define dso_local void @f25(i32 *%ptr) {
 ; CHECK-LABEL: f25:
 ; CHECK: lrl [[REG:%r[0-5]]], g3
 ; CHECK: st [[REG]], 0(%r2)
@@ -310,7 +310,7 @@ define void @f25(i32 *%ptr) {
 }
 
 ; ...likewise STRL.
-define void @f26(i32 *%ptr) {
+define dso_local void @f26(i32 *%ptr) {
 ; CHECK-LABEL: f26:
 ; CHECK: l [[REG:%r[0-5]]], 0(%r2)
 ; CHECK: strl [[REG]], g3
@@ -321,7 +321,7 @@ define void @f26(i32 *%ptr) {
 }
 
 ; Test that we use LGRL for i64.
-define void @f27(i64 *%ptr) {
+define dso_local void @f27(i64 *%ptr) {
 ; CHECK-LABEL: f27:
 ; CHECK: lgrl [[REG:%r[0-5]]], g4
 ; CHECK: stg [[REG]], 0(%r2)
@@ -332,7 +332,7 @@ define void @f27(i64 *%ptr) {
 }
 
 ; ...likewise STGRL.
-define void @f28(i64 *%ptr) {
+define dso_local void @f28(i64 *%ptr) {
 ; CHECK-LABEL: f28:
 ; CHECK: lg [[REG:%r[0-5]]], 0(%r2)
 ; CHECK: stgrl [[REG]], g4
@@ -343,7 +343,7 @@ define void @f28(i64 *%ptr) {
 }
 
 ; Test that we can use MVC for global addresses for fp128.
-define void @f29(fp128 *%ptr) {
+define dso_local void @f29(fp128 *%ptr) {
 ; CHECK-LABEL: f29:
 ; CHECK-DAG: larl [[SRC:%r[0-5]]], g5src
 ; CHECK-DAG: larl [[DST:%r[0-5]]], g5dst
@@ -355,7 +355,7 @@ define void @f29(fp128 *%ptr) {
 }
 
 ; Test a case where offset disambiguation is enough.
-define void @f30(i64 *%ptr1) {
+define dso_local void @f30(i64 *%ptr1) {
 ; CHECK-LABEL: f30:
 ; CHECK: mvc 8(8,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -366,7 +366,7 @@ define void @f30(i64 *%ptr1) {
 }
 
 ; Test f21 in cases where TBAA tells us there is no alias.
-define void @f31(i64 *%ptr1, i64 *%ptr2) {
+define dso_local void @f31(i64 *%ptr1, i64 *%ptr2) {
 ; CHECK-LABEL: f31:
 ; CHECK: mvc 0(8,%r3), 0(%r2)
 ; CHECK: br %r14
@@ -376,7 +376,7 @@ define void @f31(i64 *%ptr1, i64 *%ptr2) {
 }
 
 ; Test f21 in cases where TBAA is present but doesn't help.
-define void @f32(i64 *%ptr1, i64 *%ptr2) {
+define dso_local void @f32(i64 *%ptr1, i64 *%ptr2) {
 ; CHECK-LABEL: f32:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
diff --git a/llvm/test/CodeGen/SystemZ/pie.ll b/llvm/test/CodeGen/SystemZ/pie.ll
index 8fc2614..a3b33c4 100644
--- a/llvm/test/CodeGen/SystemZ/pie.ll
+++ b/llvm/test/CodeGen/SystemZ/pie.ll
@@ -1,8 +1,8 @@
 ; RUN: llc -mtriple=s390x-linux-gnu -relocation-model=pic < %s | FileCheck %s
 
-@foo = global i32 42
+@foo = dso_local global i32 42
 
-define i32* @get_foo() {
+define dso_local i32* @get_foo() {
   ret i32* @foo
 }
 
diff --git a/llvm/test/CodeGen/SystemZ/prefetch-01.ll b/llvm/test/CodeGen/SystemZ/prefetch-01.ll
index 8147380..f184022 100644
--- a/llvm/test/CodeGen/SystemZ/prefetch-01.ll
+++ b/llvm/test/CodeGen/SystemZ/prefetch-01.ll
@@ -4,10 +4,10 @@
 
 declare void @llvm.prefetch(i8*, i32, i32, i32)
 
-@g = global [4096 x i8] zeroinitializer
+@g = dso_local global [4096 x i8] zeroinitializer
 
 ; Check that instruction read prefetches are ignored.
-define void @f1(i8 *%ptr) {
+define dso_local void @f1(i8 *%ptr) {
 ; CHECK-LABEL: f1:
 ; CHECK-NOT: %r2
 ; CHECK: br %r14
@@ -16,7 +16,7 @@ define void @f1(i8 *%ptr) {
 }
 
 ; Check that instruction write prefetches are ignored.
-define void @f2(i8 *%ptr) {
+define dso_local void @f2(i8 *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
 ; CHECK: br %r14
@@ -25,7 +25,7 @@ define void @f2(i8 *%ptr) {
 }
 
 ; Check data read prefetches.
-define void @f3(i8 *%ptr) {
+define dso_local void @f3(i8 *%ptr) {
 ; CHECK-LABEL: f3:
 ; CHECK: pfd 1, 0(%r2)
 ; CHECK: br %r14
@@ -34,7 +34,7 @@ define void @f3(i8 *%ptr) {
 }
 
 ; Check data write prefetches.
-define void @f4(i8 *%ptr) {
+define dso_local void @f4(i8 *%ptr) {
 ; CHECK-LABEL: f4:
 ; CHECK: pfd 2, 0(%r2)
 ; CHECK: br %r14
@@ -43,7 +43,7 @@ define void @f4(i8 *%ptr) {
 }
 
 ; Check an address at the negative end of the range.
-define void @f5(i8 *%base, i64 %index) {
+define dso_local void @f5(i8 *%base, i64 %index) {
 ; CHECK-LABEL: f5:
 ; CHECK: pfd 2, -524288({{%r2,%r3|%r3,%r2}})
 ; CHECK: br %r14
@@ -54,7 +54,7 @@ define void @f5(i8 *%base, i64 %index) {
 }
 
 ; Check an address at the positive end of the range.
-define void @f6(i8 *%base, i64 %index) {
+define dso_local void @f6(i8 *%base, i64 %index) {
 ; CHECK-LABEL: f6:
 ; CHECK: pfd 2, 524287({{%r2,%r3|%r3,%r2}})
 ; CHECK: br %r14
@@ -65,7 +65,7 @@ define void @f6(i8 *%base, i64 %index) {
 }
 
 ; Check that the next address up still compiles.
-define void @f7(i8 *%base, i64 %index) {
+define dso_local void @f7(i8 *%base, i64 %index) {
 ; CHECK-LABEL: f7:
 ; CHECK: 524288
 ; CHECK: pfd 2,
@@ -77,7 +77,7 @@ define void @f7(i8 *%base, i64 %index) {
 }
 
 ; Check pc-relative prefetches.
-define void @f8() {
+define dso_local void @f8() {
 ; CHECK-LABEL: f8:
 ; CHECK: pfdrl 2, g
 ; CHECK: br %r14
diff --git a/llvm/test/CodeGen/SystemZ/spill-01.ll b/llvm/test/CodeGen/SystemZ/spill-01.ll
index a2febe9..ea9a78c 100644
--- a/llvm/test/CodeGen/SystemZ/spill-01.ll
+++ b/llvm/test/CodeGen/SystemZ/spill-01.ll
@@ -5,30 +5,30 @@
 
 declare void @foo()
 
-@g0 = global i32 0
-@g1 = global i32 1
-@g2 = global i32 2
-@g3 = global i32 3
-@g4 = global i32 4
-@g5 = global i32 5
-@g6 = global i32 6
-@g7 = global i32 7
-@g8 = global i32 8
-@g9 = global i32 9
-
-@h0 = global i64 0
-@h1 = global i64 1
-@h2 = global i64 2
-@h3 = global i64 3
-@h4 = global i64 4
-@h5 = global i64 5
-@h6 = global i64 6
-@h7 = global i64 7
-@h8 = global i64 8
-@h9 = global i64 9
+@g0 = dso_local global i32 0
+@g1 = dso_local global i32 1
+@g2 = dso_local global i32 2
+@g3 = dso_local global i32 3
+@g4 = dso_local global i32 4
+@g5 = dso_local global i32 5
+@g6 = dso_local global i32 6
+@g7 = dso_local global i32 7
+@g8 = dso_local global i32 8
+@g9 = dso_local global i32 9
+
+@h0 = dso_local global i64 0
+@h1 = dso_local global i64 1
+@h2 = dso_local global i64 2
+@h3 = dso_local global i64 3
+@h4 = dso_local global i64 4
+@h5 = dso_local global i64 5
+@h6 = dso_local global i64 6
+@h7 = dso_local global i64 7
+@h8 = dso_local global i64 8
+@h9 = dso_local global i64 9
 
 ; This function shouldn't spill anything
-define void @f1(i32 *%ptr0) {
+define dso_local void @f1(i32 *%ptr0) {
 ; CHECK-LABEL: f1:
 ; CHECK: stmg
 ; CHECK: aghi %r15, -160
@@ -67,7 +67,7 @@ define void @f1(i32 *%ptr0) {
 
 ; Test a case where at least one i32 load and at least one i32 store
 ; need spills.
-define void @f2(i32 *%ptr0) {
+define dso_local void @f2(i32 *%ptr0) {
 ; CHECK-LABEL: f2:
 ; CHECK: mvc [[OFFSET1:16[04]]](4,%r15), [[OFFSET2:[0-9]+]]({{%r[0-9]+}})
 ; CHECK: brasl %r14, foo@PLT
@@ -109,7 +109,7 @@ define void @f2(i32 *%ptr0) {
 
 ; Test a case where at least one i64 load and at least one i64 store
 ; need spills.
-define void @f3(i64 *%ptr0) {
+define dso_local void @f3(i64 *%ptr0) {
 ; CHECK-LABEL: f3:
 ; CHECK: mvc 160(8,%r15), [[OFFSET:[0-9]+]]({{%r[0-9]+}})
 ; CHECK: brasl %r14, foo@PLT
@@ -154,7 +154,7 @@ define void @f3(i64 *%ptr0) {
 ; need spills.  The 8 call-saved FPRs could be used for 8 of the %vals
 ; (and are at the time of writing), but it would really be better to use
 ; MVC for all 10.
-define void @f4(float *%ptr0) {
+define dso_local void @f4(float *%ptr0) {
 ; CHECK-LABEL: f4:
 ; CHECK: mvc [[OFFSET1:16[04]]](4,%r15), [[OFFSET2:[0-9]+]]({{%r[0-9]+}})
 ; CHECK: brasl %r14, foo@PLT
@@ -198,7 +198,7 @@ define void @f4(float *%ptr0) {
 }
 
 ; Similarly for f64.
-define void @f5(double *%ptr0) {
+define dso_local void @f5(double *%ptr0) {
 ; CHECK-LABEL: f5:
 ; CHECK: mvc 160(8,%r15), [[OFFSET:[0-9]+]]({{%r[0-9]+}})
 ; CHECK: brasl %r14, foo@PLT
@@ -242,7 +242,7 @@ define void @f5(double *%ptr0) {
 }
 
 ; Repeat f2 with atomic accesses.  We shouldn't use MVC here.
-define void @f6(i32 *%ptr0) {
+define dso_local void @f6(i32 *%ptr0) {
 ; CHECK-LABEL: f6:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
@@ -281,7 +281,7 @@ define void @f6(i32 *%ptr0) {
 }
 
 ; ...likewise volatile accesses.
-define void @f7(i32 *%ptr0) {
+define dso_local void @f7(i32 *%ptr0) {
 ; CHECK-LABEL: f7:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
@@ -320,7 +320,7 @@ define void @f7(i32 *%ptr0) {
 }
 
 ; Check that LRL and STRL are not converted.
-define void @f8() {
+define dso_local void @f8() {
 ; CHECK-LABEL: f8:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
@@ -352,7 +352,7 @@ define void @f8() {
 }
 
 ; Likewise LGRL and STGRL.
-define void @f9() {
+define dso_local void @f9() {
 ; CHECK-LABEL: f9:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
@@ -388,7 +388,7 @@ define void @f9() {
 ; has two frame index operands.  Stack coloring chose a valid renumbering
 ; [FI0, FI1] -> [FI1, FI2], but applied it in the form FI0 -> FI1 -> FI2,
 ; so that both operands ended up being the same.
-define void @f10() {
+define dso_local void @f10() {
 ; CHECK-LABEL: f10:
 ; CHECK: lgrl [[REG:%r[0-9]+]], h9
 ; CHECK: stg [[REG]], [[VAL9:[0-9]+]](%r15)
@@ -459,7 +459,7 @@ skip:
 }
 
 ; This used to generate a no-op MVC.  It is very sensitive to spill heuristics.
-define void @f11() {
+define dso_local void @f11() {
 ; CHECK-LABEL: f11:
 ; CHECK-NOT: mvc [[OFFSET:[0-9]+]](8,%r15), [[OFFSET]](%r15)
 ; CHECK: br %r14
diff --git a/llvm/test/CodeGen/SystemZ/tls-01.ll b/llvm/test/CodeGen/SystemZ/tls-01.ll
index b5ffc0b..cff676b 100644
--- a/llvm/test/CodeGen/SystemZ/tls-01.ll
+++ b/llvm/test/CodeGen/SystemZ/tls-01.ll
@@ -3,11 +3,11 @@
 ; RUN: llc < %s -mcpu=z10 -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-MAIN
 ; RUN: llc < %s -mcpu=z10 -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-CP
 
-@x = thread_local global i32 0
+@x = dso_local thread_local global i32 0
 
 ; The offset must be loaded from the constant pool.  It doesn't really
 ; matter whether we use LARL/AG or LGRL/AGR for the last part.
-define i32 *@foo() {
+define dso_local i32 *@foo() {
 ; CHECK-CP: .LCP{{.*}}:
 ; CHECK-CP: .quad x@NTPOFF
 ;
-- 
2.7.4