From a90530f7c108afc61af9b1d4c57d8fe62cf25908 Mon Sep 17 00:00:00 2001 From: Sander de Smalen Date: Wed, 11 Jul 2018 10:08:00 +0000 Subject: [PATCH] [AArch64][SVE] Asm: Support for LAST(A|B) and CLAST(A|B) instructions. The LASTB and LASTA instructions extract the last active element, or element after the last active, from the source vector. The added variants are: Scalar: last(a|b) w0, p0, z0.b last(a|b) w0, p0, z0.h last(a|b) w0, p0, z0.s last(a|b) x0, p0, z0.d SIMD & FP Scalar: last(a|b) b0, p0, z0.b last(a|b) h0, p0, z0.h last(a|b) s0, p0, z0.s last(a|b) d0, p0, z0.d The CLASTB and CLASTA conditionally extract the last or element after the last active element from the source vector. The added variants are: Scalar: clast(a|b) w0, p0, w0, z0.b clast(a|b) w0, p0, w0, z0.h clast(a|b) w0, p0, w0, z0.s clast(a|b) x0, p0, x0, z0.d SIMD & FP Scalar: clast(a|b) b0, p0, b0, z0.b clast(a|b) h0, p0, h0, z0.h clast(a|b) s0, p0, s0, z0.s clast(a|b) d0, p0, d0, z0.d Vector: clast(a|b) z0.b, p0, z0.b, z1.b clast(a|b) z0.h, p0, z0.h, z1.h clast(a|b) z0.s, p0, z0.s, z1.s clast(a|b) z0.d, p0, z0.d, z1.d Please refer to the architecture specification for more details on the semantics of the added instructions. llvm-svn: 336783 --- llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 12 +++ llvm/lib/Target/AArch64/SVEInstrFormats.td | 136 +++++++++++++++++++++++++ llvm/test/MC/AArch64/SVE/clasta-diagnostics.s | 79 ++++++++++++++ llvm/test/MC/AArch64/SVE/clasta.s | 80 +++++++++++++++ llvm/test/MC/AArch64/SVE/clastb-diagnostics.s | 79 ++++++++++++++ llvm/test/MC/AArch64/SVE/clastb.s | 80 +++++++++++++++ llvm/test/MC/AArch64/SVE/lasta-diagnostics.s | 54 ++++++++++ llvm/test/MC/AArch64/SVE/lasta.s | 56 ++++++++++ llvm/test/MC/AArch64/SVE/lastb-diagnostics.s | 54 ++++++++++ llvm/test/MC/AArch64/SVE/lastb.s | 56 ++++++++++ 10 files changed, 686 insertions(+) create mode 100644 llvm/test/MC/AArch64/SVE/clasta-diagnostics.s create mode 100644 llvm/test/MC/AArch64/SVE/clasta.s create mode 100644 llvm/test/MC/AArch64/SVE/clastb-diagnostics.s create mode 100644 llvm/test/MC/AArch64/SVE/clastb.s create mode 100644 llvm/test/MC/AArch64/SVE/lasta-diagnostics.s create mode 100644 llvm/test/MC/AArch64/SVE/lasta.s create mode 100644 llvm/test/MC/AArch64/SVE/lastb-diagnostics.s create mode 100644 llvm/test/MC/AArch64/SVE/lastb.s diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 6ae55aa..d747d76 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -128,6 +128,18 @@ let Predicates = [HasSVE] in { def NORS_PPzPP : sve_int_pred_log<0b1110, "nors">; def NANDS_PPzPP : sve_int_pred_log<0b1111, "nands">; + defm CLASTA_RPZ : sve_int_perm_clast_rz<0, "clasta">; + defm CLASTB_RPZ : sve_int_perm_clast_rz<1, "clastb">; + defm CLASTA_VPZ : sve_int_perm_clast_vz<0, "clasta">; + defm CLASTB_VPZ : sve_int_perm_clast_vz<1, "clastb">; + defm CLASTA_ZPZ : sve_int_perm_clast_zz<0, "clasta">; + defm CLASTB_ZPZ : sve_int_perm_clast_zz<1, "clastb">; + + defm LASTA_RPZ : sve_int_perm_last_r<0, "lasta">; + defm LASTB_RPZ : sve_int_perm_last_r<1, "lastb">; + defm LASTA_VPZ : sve_int_perm_last_v<0, "lasta">; + defm LASTB_VPZ : sve_int_perm_last_v<1, "lastb">; + // continuous load with reg+immediate defm LD1B_IMM : sve_mem_cld_si<0b0000, "ld1b", Z_b, ZPR8>; defm LD1B_H_IMM : sve_mem_cld_si<0b0001, "ld1b", Z_h, ZPR16>; diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index b3f7137..b8e67f6 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -2368,6 +2368,142 @@ class sve_int_setffr // SVE Permute Vector - Predicated Group //===----------------------------------------------------------------------===// +class sve_int_perm_clast_rz sz8_64, bit ab, string asm, + ZPRRegOp zprty, RegisterClass rt> +: I<(outs rt:$Rdn), (ins PPR3bAny:$Pg, rt:$_Rdn, zprty:$Zm), + asm, "\t$Rdn, $Pg, $_Rdn, $Zm", + "", + []>, Sched<[]> { + bits<3> Pg; + bits<5> Rdn; + bits<5> Zm; + let Inst{31-24} = 0b00000101; + let Inst{23-22} = sz8_64; + let Inst{21-17} = 0b11000; + let Inst{16} = ab; + let Inst{15-13} = 0b101; + let Inst{12-10} = Pg; + let Inst{9-5} = Zm; + let Inst{4-0} = Rdn; + + let Constraints = "$Rdn = $_Rdn"; +} + +multiclass sve_int_perm_clast_rz { + def _B : sve_int_perm_clast_rz<0b00, ab, asm, ZPR8, GPR32>; + def _H : sve_int_perm_clast_rz<0b01, ab, asm, ZPR16, GPR32>; + def _S : sve_int_perm_clast_rz<0b10, ab, asm, ZPR32, GPR32>; + def _D : sve_int_perm_clast_rz<0b11, ab, asm, ZPR64, GPR64>; +} + +class sve_int_perm_clast_vz sz8_64, bit ab, string asm, + ZPRRegOp zprty, RegisterClass rt> +: I<(outs rt:$Vdn), (ins PPR3bAny:$Pg, rt:$_Vdn, zprty:$Zm), + asm, "\t$Vdn, $Pg, $_Vdn, $Zm", + "", + []>, Sched<[]> { + bits<3> Pg; + bits<5> Vdn; + bits<5> Zm; + let Inst{31-24} = 0b00000101; + let Inst{23-22} = sz8_64; + let Inst{21-17} = 0b10101; + let Inst{16} = ab; + let Inst{15-13} = 0b100; + let Inst{12-10} = Pg; + let Inst{9-5} = Zm; + let Inst{4-0} = Vdn; + + let Constraints = "$Vdn = $_Vdn"; +} + +multiclass sve_int_perm_clast_vz { + def _B : sve_int_perm_clast_vz<0b00, ab, asm, ZPR8, FPR8>; + def _H : sve_int_perm_clast_vz<0b01, ab, asm, ZPR16, FPR16>; + def _S : sve_int_perm_clast_vz<0b10, ab, asm, ZPR32, FPR32>; + def _D : sve_int_perm_clast_vz<0b11, ab, asm, ZPR64, FPR64>; +} + +class sve_int_perm_clast_zz sz8_64, bit ab, string asm, + ZPRRegOp zprty> +: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm), + asm, "\t$Zdn, $Pg, $_Zdn, $Zm", + "", + []>, Sched<[]> { + bits<3> Pg; + bits<5> Zdn; + bits<5> Zm; + let Inst{31-24} = 0b00000101; + let Inst{23-22} = sz8_64; + let Inst{21-17} = 0b10100; + let Inst{16} = ab; + let Inst{15-13} = 0b100; + let Inst{12-10} = Pg; + let Inst{9-5} = Zm; + let Inst{4-0} = Zdn; + + let Constraints = "$Zdn = $_Zdn"; +} + +multiclass sve_int_perm_clast_zz { + def _B : sve_int_perm_clast_zz<0b00, ab, asm, ZPR8>; + def _H : sve_int_perm_clast_zz<0b01, ab, asm, ZPR16>; + def _S : sve_int_perm_clast_zz<0b10, ab, asm, ZPR32>; + def _D : sve_int_perm_clast_zz<0b11, ab, asm, ZPR64>; +} + +class sve_int_perm_last_r sz8_64, bit ab, string asm, + ZPRRegOp zprty, RegisterClass resultRegType> +: I<(outs resultRegType:$Rd), (ins PPR3bAny:$Pg, zprty:$Zn), + asm, "\t$Rd, $Pg, $Zn", + "", + []>, Sched<[]> { + bits<3> Pg; + bits<5> Rd; + bits<5> Zn; + let Inst{31-24} = 0b00000101; + let Inst{23-22} = sz8_64; + let Inst{21-17} = 0b10000; + let Inst{16} = ab; + let Inst{15-13} = 0b101; + let Inst{12-10} = Pg; + let Inst{9-5} = Zn; + let Inst{4-0} = Rd; +} + +multiclass sve_int_perm_last_r { + def _B : sve_int_perm_last_r<0b00, ab, asm, ZPR8, GPR32>; + def _H : sve_int_perm_last_r<0b01, ab, asm, ZPR16, GPR32>; + def _S : sve_int_perm_last_r<0b10, ab, asm, ZPR32, GPR32>; + def _D : sve_int_perm_last_r<0b11, ab, asm, ZPR64, GPR64>; +} + +class sve_int_perm_last_v sz8_64, bit ab, string asm, + ZPRRegOp zprty, RegisterClass dstRegtype> +: I<(outs dstRegtype:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn), + asm, "\t$Vd, $Pg, $Zn", + "", + []>, Sched<[]> { + bits<3> Pg; + bits<5> Vd; + bits<5> Zn; + let Inst{31-24} = 0b00000101; + let Inst{23-22} = sz8_64; + let Inst{21-17} = 0b10001; + let Inst{16} = ab; + let Inst{15-13} = 0b100; + let Inst{12-10} = Pg; + let Inst{9-5} = Zn; + let Inst{4-0} = Vd; +} + +multiclass sve_int_perm_last_v { + def _B : sve_int_perm_last_v<0b00, ab, asm, ZPR8, FPR8>; + def _H : sve_int_perm_last_v<0b01, ab, asm, ZPR16, FPR16>; + def _S : sve_int_perm_last_v<0b10, ab, asm, ZPR32, FPR32>; + def _D : sve_int_perm_last_v<0b11, ab, asm, ZPR64, FPR64>; +} + class sve_int_perm_cpy_r sz8_64, string asm, ZPRRegOp zprty, RegisterClass srcRegType> : I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, srcRegType:$Rn), diff --git a/llvm/test/MC/AArch64/SVE/clasta-diagnostics.s b/llvm/test/MC/AArch64/SVE/clasta-diagnostics.s new file mode 100644 index 0000000..cfc1db1 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/clasta-diagnostics.s @@ -0,0 +1,79 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid predicate + +clasta w0, p8, w0, z31.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: clasta w0, p8, w0, z31.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid element width + +clasta w0, p7, x0, z31.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: clasta w0, p7, x0, z31.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +clasta x0, p7, x0, z31.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: clasta x0, p7, x0, z31.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +clasta x0, p7, x0, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: clasta x0, p7, x0, z31.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +clasta x0, p7, x0, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: clasta x0, p7, x0, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +clasta w0, p7, w0, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: clasta w0, p7, w0, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +clasta b0, p7, b0, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: clasta b0, p7, b0, z31.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +clasta h0, p7, h0, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: clasta h0, p7, h0, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +clasta s0, p7, s0, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: clasta s0, p7, s0, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +clasta d0, p7, d0, z31.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: clasta d0, p7, d0, z31.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +clasta z0.b, p7, z0.b, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: clasta z0.b, p7, z0.b, z31.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +clasta z0.h, p7, z0.h, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: clasta z0.h, p7, z0.h, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +clasta z0.s, p7, z0.s, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: clasta z0.s, p7, z0.s, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +clasta z0.d, p7, z0.d, z31.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: clasta z0.d, p7, z0.d, z31.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/clasta.s b/llvm/test/MC/AArch64/SVE/clasta.s new file mode 100644 index 0000000..3e12031 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/clasta.s @@ -0,0 +1,80 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +clasta w0, p7, w0, z31.b +// CHECK-INST: clasta w0, p7, w0, z31.b +// CHECK-ENCODING: [0xe0,0xbf,0x30,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bf 30 05 + +clasta w0, p7, w0, z31.h +// CHECK-INST: clasta w0, p7, w0, z31.h +// CHECK-ENCODING: [0xe0,0xbf,0x70,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bf 70 05 + +clasta w0, p7, w0, z31.s +// CHECK-INST: clasta w0, p7, w0, z31.s +// CHECK-ENCODING: [0xe0,0xbf,0xb0,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bf b0 05 + +clasta x0, p7, x0, z31.d +// CHECK-INST: clasta x0, p7, x0, z31.d +// CHECK-ENCODING: [0xe0,0xbf,0xf0,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bf f0 05 + +clasta b0, p7, b0, z31.b +// CHECK-INST: clasta b0, p7, b0, z31.b +// CHECK-ENCODING: [0xe0,0x9f,0x2a,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f 2a 05 + +clasta h0, p7, h0, z31.h +// CHECK-INST: clasta h0, p7, h0, z31.h +// CHECK-ENCODING: [0xe0,0x9f,0x6a,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f 6a 05 + +clasta s0, p7, s0, z31.s +// CHECK-INST: clasta s0, p7, s0, z31.s +// CHECK-ENCODING: [0xe0,0x9f,0xaa,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f aa 05 + +clasta d0, p7, d0, z31.d +// CHECK-INST: clasta d0, p7, d0, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xea,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f ea 05 + +clasta z0.b, p7, z0.b, z31.b +// CHECK-INST: clasta z0.b, p7, z0.b, z31.b +// CHECK-ENCODING: [0xe0,0x9f,0x28,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f 28 05 + +clasta z0.h, p7, z0.h, z31.h +// CHECK-INST: clasta z0.h, p7, z0.h, z31.h +// CHECK-ENCODING: [0xe0,0x9f,0x68,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f 68 05 + +clasta z0.s, p7, z0.s, z31.s +// CHECK-INST: clasta z0.s, p7, z0.s, z31.s +// CHECK-ENCODING: [0xe0,0x9f,0xa8,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f a8 05 + +clasta z0.d, p7, z0.d, z31.d +// CHECK-INST: clasta z0.d, p7, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xe8,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f e8 05 diff --git a/llvm/test/MC/AArch64/SVE/clastb-diagnostics.s b/llvm/test/MC/AArch64/SVE/clastb-diagnostics.s new file mode 100644 index 0000000..62f6964 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/clastb-diagnostics.s @@ -0,0 +1,79 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid predicate + +clastb w0, p8, w0, z31.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: clastb w0, p8, w0, z31.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid element width + +clastb w0, p7, x0, z31.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: clastb w0, p7, x0, z31.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +clastb x0, p7, x0, z31.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: clastb x0, p7, x0, z31.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +clastb x0, p7, x0, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: clastb x0, p7, x0, z31.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +clastb x0, p7, x0, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: clastb x0, p7, x0, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +clastb w0, p7, w0, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: clastb w0, p7, w0, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +clastb b0, p7, b0, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: clastb b0, p7, b0, z31.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +clastb h0, p7, h0, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: clastb h0, p7, h0, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +clastb s0, p7, s0, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: clastb s0, p7, s0, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +clastb d0, p7, d0, z31.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: clastb d0, p7, d0, z31.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +clastb z0.b, p7, z0.b, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: clastb z0.b, p7, z0.b, z31.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +clastb z0.h, p7, z0.h, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: clastb z0.h, p7, z0.h, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +clastb z0.s, p7, z0.s, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: clastb z0.s, p7, z0.s, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +clastb z0.d, p7, z0.d, z31.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: clastb z0.d, p7, z0.d, z31.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/clastb.s b/llvm/test/MC/AArch64/SVE/clastb.s new file mode 100644 index 0000000..654ab11 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/clastb.s @@ -0,0 +1,80 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +clastb w0, p7, w0, z31.b +// CHECK-INST: clastb w0, p7, w0, z31.b +// CHECK-ENCODING: [0xe0,0xbf,0x31,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bf 31 05 + +clastb w0, p7, w0, z31.h +// CHECK-INST: clastb w0, p7, w0, z31.h +// CHECK-ENCODING: [0xe0,0xbf,0x71,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bf 71 05 + +clastb w0, p7, w0, z31.s +// CHECK-INST: clastb w0, p7, w0, z31.s +// CHECK-ENCODING: [0xe0,0xbf,0xb1,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bf b1 05 + +clastb x0, p7, x0, z31.d +// CHECK-INST: clastb x0, p7, x0, z31.d +// CHECK-ENCODING: [0xe0,0xbf,0xf1,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bf f1 05 + +clastb b0, p7, b0, z31.b +// CHECK-INST: clastb b0, p7, b0, z31.b +// CHECK-ENCODING: [0xe0,0x9f,0x2b,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f 2b 05 + +clastb h0, p7, h0, z31.h +// CHECK-INST: clastb h0, p7, h0, z31.h +// CHECK-ENCODING: [0xe0,0x9f,0x6b,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f 6b 05 + +clastb s0, p7, s0, z31.s +// CHECK-INST: clastb s0, p7, s0, z31.s +// CHECK-ENCODING: [0xe0,0x9f,0xab,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f ab 05 + +clastb d0, p7, d0, z31.d +// CHECK-INST: clastb d0, p7, d0, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xeb,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f eb 05 + +clastb z0.b, p7, z0.b, z31.b +// CHECK-INST: clastb z0.b, p7, z0.b, z31.b +// CHECK-ENCODING: [0xe0,0x9f,0x29,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f 29 05 + +clastb z0.h, p7, z0.h, z31.h +// CHECK-INST: clastb z0.h, p7, z0.h, z31.h +// CHECK-ENCODING: [0xe0,0x9f,0x69,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f 69 05 + +clastb z0.s, p7, z0.s, z31.s +// CHECK-INST: clastb z0.s, p7, z0.s, z31.s +// CHECK-ENCODING: [0xe0,0x9f,0xa9,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f a9 05 + +clastb z0.d, p7, z0.d, z31.d +// CHECK-INST: clastb z0.d, p7, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xe9,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f e9 05 diff --git a/llvm/test/MC/AArch64/SVE/lasta-diagnostics.s b/llvm/test/MC/AArch64/SVE/lasta-diagnostics.s new file mode 100644 index 0000000..dd81555 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/lasta-diagnostics.s @@ -0,0 +1,54 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid predicate + +lasta w0, p8, z31.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: lasta w0, p8, z31.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid element width + +lasta x0, p7, z31.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: lasta x0, p7, z31.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +lasta x0, p7, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: lasta x0, p7, z31.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +lasta x0, p7, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: lasta x0, p7, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +lasta w0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: lasta w0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +lasta b0, p7, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: lasta b0, p7, z31.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +lasta h0, p7, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: lasta h0, p7, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +lasta s0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: lasta s0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +lasta d0, p7, z31.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: lasta d0, p7, z31.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/lasta.s b/llvm/test/MC/AArch64/SVE/lasta.s new file mode 100644 index 0000000..7d17ab2 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/lasta.s @@ -0,0 +1,56 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +lasta w0, p7, z31.b +// CHECK-INST: lasta w0, p7, z31.b +// CHECK-ENCODING: [0xe0,0xbf,0x20,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bf 20 05 + +lasta w0, p7, z31.h +// CHECK-INST: lasta w0, p7, z31.h +// CHECK-ENCODING: [0xe0,0xbf,0x60,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bf 60 05 + +lasta w0, p7, z31.s +// CHECK-INST: lasta w0, p7, z31.s +// CHECK-ENCODING: [0xe0,0xbf,0xa0,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bf a0 05 + +lasta x0, p7, z31.d +// CHECK-INST: lasta x0, p7, z31.d +// CHECK-ENCODING: [0xe0,0xbf,0xe0,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bf e0 05 + +lasta b0, p7, z31.b +// CHECK-INST: lasta b0, p7, z31.b +// CHECK-ENCODING: [0xe0,0x9f,0x22,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f 22 05 + +lasta h0, p7, z31.h +// CHECK-INST: lasta h0, p7, z31.h +// CHECK-ENCODING: [0xe0,0x9f,0x62,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f 62 05 + +lasta s0, p7, z31.s +// CHECK-INST: lasta s0, p7, z31.s +// CHECK-ENCODING: [0xe0,0x9f,0xa2,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f a2 05 + +lasta d0, p7, z31.d +// CHECK-INST: lasta d0, p7, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xe2,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f e2 05 diff --git a/llvm/test/MC/AArch64/SVE/lastb-diagnostics.s b/llvm/test/MC/AArch64/SVE/lastb-diagnostics.s new file mode 100644 index 0000000..ed92c76 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/lastb-diagnostics.s @@ -0,0 +1,54 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid predicate + +lastb w0, p8, z31.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: lastb w0, p8, z31.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid element width + +lastb x0, p7, z31.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: lastb x0, p7, z31.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +lastb x0, p7, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: lastb x0, p7, z31.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +lastb x0, p7, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: lastb x0, p7, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +lastb w0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: lastb w0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +lastb b0, p7, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: lastb b0, p7, z31.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +lastb h0, p7, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: lastb h0, p7, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +lastb s0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: lastb s0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +lastb d0, p7, z31.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: lastb d0, p7, z31.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/lastb.s b/llvm/test/MC/AArch64/SVE/lastb.s new file mode 100644 index 0000000..2589d66 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/lastb.s @@ -0,0 +1,56 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +lastb w0, p7, z31.b +// CHECK-INST: lastb w0, p7, z31.b +// CHECK-ENCODING: [0xe0,0xbf,0x21,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bf 21 05 + +lastb w0, p7, z31.h +// CHECK-INST: lastb w0, p7, z31.h +// CHECK-ENCODING: [0xe0,0xbf,0x61,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bf 61 05 + +lastb w0, p7, z31.s +// CHECK-INST: lastb w0, p7, z31.s +// CHECK-ENCODING: [0xe0,0xbf,0xa1,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bf a1 05 + +lastb x0, p7, z31.d +// CHECK-INST: lastb x0, p7, z31.d +// CHECK-ENCODING: [0xe0,0xbf,0xe1,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bf e1 05 + +lastb b0, p7, z31.b +// CHECK-INST: lastb b0, p7, z31.b +// CHECK-ENCODING: [0xe0,0x9f,0x23,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f 23 05 + +lastb h0, p7, z31.h +// CHECK-INST: lastb h0, p7, z31.h +// CHECK-ENCODING: [0xe0,0x9f,0x63,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f 63 05 + +lastb s0, p7, z31.s +// CHECK-INST: lastb s0, p7, z31.s +// CHECK-ENCODING: [0xe0,0x9f,0xa3,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f a3 05 + +lastb d0, p7, z31.d +// CHECK-INST: lastb d0, p7, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xe3,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f e3 05 -- 2.7.4