From a9021d348e82f220419b38bc34bc86a2c650ce30 Mon Sep 17 00:00:00 2001 From: SooChan Lim Date: Thu, 30 Mar 2017 17:39:48 +0900 Subject: [PATCH] Revert "use g_enable_cache_ctrl for cache control" This reverts commit 0e66ca6fb96f3e0940a985c94ac65f7e5fedd072. Change-Id: Ie7ac32be0cf6546f17ff21f6fa94620ecda04efe --- src/tbm_bufmgr_exynos.c | 47 +++++++++++++++++------------------------------ src/tbm_bufmgr_tgl.h | 5 +++++ 2 files changed, 22 insertions(+), 30 deletions(-) diff --git a/src/tbm_bufmgr_exynos.c b/src/tbm_bufmgr_exynos.c index a9803a5..479192e 100644 --- a/src/tbm_bufmgr_exynos.c +++ b/src/tbm_bufmgr_exynos.c @@ -146,9 +146,6 @@ static unsigned int g_tbm_surface_alignment_pitch_rgb; } \ } -/* cache control at backend */ -static unsigned int g_enable_cache_ctrl = 0; - struct dma_buf_info { unsigned long size; unsigned int fence_supported; @@ -267,6 +264,7 @@ uint32_t tbm_exynos_color_format_list[TBM_COLOR_FORMAT_COUNT] = { TBM_FORMAT_YUV420 }; +#ifdef ENABLE_CACHECTRL #ifdef TGL_GET_VERSION static inline int _tgl_get_version(int fd) @@ -465,14 +463,12 @@ _exynos_cache_flush(tbm_bufmgr_exynos bufmgr_exynos, tbm_bo_exynos bo_exynos, in return 1; } +#endif static int _bo_init_cache_state(tbm_bufmgr_exynos bufmgr_exynos, tbm_bo_exynos bo_exynos, int import) { - /* check whether cache control do or not */ - if (!g_enable_cache_ctrl) - return 1; - +#ifdef ENABLE_CACHECTRL EXYNOS_RETURN_VAL_IF_FAIL(bufmgr_exynos != NULL, 0); EXYNOS_RETURN_VAL_IF_FAIL(bo_exynos != NULL, 0); @@ -490,6 +486,7 @@ _bo_init_cache_state(tbm_bufmgr_exynos bufmgr_exynos, tbm_bo_exynos bo_exynos, i _tgl_set_data(bufmgr_exynos->tgl_fd, bo_exynos->name, cache_state.val); } +#endif return 1; } @@ -497,10 +494,7 @@ _bo_init_cache_state(tbm_bufmgr_exynos bufmgr_exynos, tbm_bo_exynos bo_exynos, i static int _bo_set_cache_state(tbm_bufmgr_exynos bufmgr_exynos, tbm_bo_exynos bo_exynos, int device, int opt) { - /* check whether cache control do or not */ - if (!g_enable_cache_ctrl) - return 1; - +#ifdef ENABLE_CACHECTRL EXYNOS_RETURN_VAL_IF_FAIL(bufmgr_exynos != NULL, 0); EXYNOS_RETURN_VAL_IF_FAIL(bo_exynos != NULL, 0); @@ -559,6 +553,7 @@ _bo_set_cache_state(tbm_bufmgr_exynos bufmgr_exynos, tbm_bo_exynos bo_exynos, in need_flush, cntFlush); } +#endif return 1; } @@ -566,10 +561,7 @@ _bo_set_cache_state(tbm_bufmgr_exynos bufmgr_exynos, tbm_bo_exynos bo_exynos, in static int _bo_save_cache_state(tbm_bufmgr_exynos bufmgr_exynos, tbm_bo_exynos bo_exynos) { - /* check whether cache control do or not */ - if (!g_enable_cache_ctrl) - return 1; - +#ifdef ENABLE_CACHECTRL EXYNOS_RETURN_VAL_IF_FAIL(bufmgr_exynos != NULL, 0); EXYNOS_RETURN_VAL_IF_FAIL(bo_exynos != NULL, 0); @@ -585,6 +577,7 @@ _bo_save_cache_state(tbm_bufmgr_exynos bufmgr_exynos, tbm_bo_exynos bo_exynos) bo_exynos->cache_state.data.cntFlush = cntFlush; _tgl_set_data(bufmgr_exynos->tgl_fd, bo_exynos->name, bo_exynos->cache_state.val); +#endif return 1; } @@ -592,10 +585,7 @@ _bo_save_cache_state(tbm_bufmgr_exynos bufmgr_exynos, tbm_bo_exynos bo_exynos) static void _bo_destroy_cache_state(tbm_bufmgr_exynos bufmgr_exynos, tbm_bo_exynos bo_exynos) { - /* check whether cache control do or not */ - if (!g_enable_cache_ctrl) - return; - +#ifdef ENABLE_CACHECTRL EXYNOS_RETURN_IF_FAIL(bufmgr_exynos != NULL); EXYNOS_RETURN_IF_FAIL(bo_exynos != NULL); @@ -603,15 +593,13 @@ _bo_destroy_cache_state(tbm_bufmgr_exynos bufmgr_exynos, tbm_bo_exynos bo_exynos return ; _tgl_destroy(bufmgr_exynos->tgl_fd, bo_exynos->name); +#endif } static int _bufmgr_init_cache_state(tbm_bufmgr_exynos bufmgr_exynos) { - /* check whether cache control do or not */ - if (!g_enable_cache_ctrl) - return 1; - +#ifdef ENABLE_CACHECTRL EXYNOS_RETURN_VAL_IF_FAIL(bufmgr_exynos != NULL, 0); if (bufmgr_exynos->use_dma_fence) @@ -642,6 +630,7 @@ _bufmgr_init_cache_state(tbm_bufmgr_exynos bufmgr_exynos) close(bufmgr_exynos->tgl_fd); return 0; } +#endif return 1; } @@ -649,10 +638,7 @@ _bufmgr_init_cache_state(tbm_bufmgr_exynos bufmgr_exynos) static void _bufmgr_deinit_cache_state(tbm_bufmgr_exynos bufmgr_exynos) { - /* check whether cache control do or not */ - if (!g_enable_cache_ctrl) - return; - +#ifdef ENABLE_CACHECTRL EXYNOS_RETURN_IF_FAIL(bufmgr_exynos != NULL); if (bufmgr_exynos->use_dma_fence) @@ -660,6 +646,7 @@ _bufmgr_deinit_cache_state(tbm_bufmgr_exynos bufmgr_exynos) if (bufmgr_exynos->tgl_fd >= 0) close(bufmgr_exynos->tgl_fd); +#endif } static int @@ -1507,9 +1494,10 @@ tbm_exynos_bo_unmap(tbm_bo bo) if (bo_exynos->map_cnt == 0) _bo_save_cache_state(bufmgr_exynos, bo_exynos); - /* check whether cache control do or not */ - if (g_enable_cache_ctrl && bo_exynos->last_map_device == TBM_DEVICE_CPU) +#ifdef ENABLE_CACHECTRL + if (bo_exynos->last_map_device == TBM_DEVICE_CPU) _exynos_cache_flush(bufmgr_exynos, bo_exynos, TBM_EXYNOS_CACHE_FLUSH_ALL); +#endif bo_exynos->last_map_device = -1; @@ -2252,7 +2240,6 @@ init_tbm_bufmgr_priv(tbm_bufmgr bufmgr, int fd) if (!strncmp(value, "TW1", 4)) { g_tbm_surface_alignment_plane = 8; g_tbm_surface_alignment_pitch_rgb = 8; - g_enable_cache_ctrl = 1; } else { g_tbm_surface_alignment_plane = 64; g_tbm_surface_alignment_pitch_rgb = 64; diff --git a/src/tbm_bufmgr_tgl.h b/src/tbm_bufmgr_tgl.h index b442f73..0ad453c 100644 --- a/src/tbm_bufmgr_tgl.h +++ b/src/tbm_bufmgr_tgl.h @@ -34,8 +34,10 @@ #include +#ifdef ENABLE_CACHECTRL static char tgl_devfile[] = "/dev/slp_global_lock"; static char tgl_devfile1[] = "/dev/tgl"; +#endif #define TGL_IOCTL_BASE 0x32 #define TGL_IO(nr) _IO(TGL_IOCTL_BASE, nr) @@ -123,6 +125,7 @@ enum { /* get user data with key */ #define TGL_IOCTL_GET_DATA TGL_IOR(_TGL_GET_DATA, struct tgl_usr_data) +#ifdef ENABLE_CACHECTRL /* indicate cache units. */ enum e_drm_exynos_gem_cache_sel { EXYNOS_DRM_L1_CACHE = 1 << 0, @@ -172,4 +175,6 @@ struct drm_exynos_gem_cache_op { #define DRM_IOCTL_EXYNOS_GEM_CACHE_OP DRM_IOWR(DRM_COMMAND_BASE + \ DRM_EXYNOS_GEM_CACHE_OP, struct drm_exynos_gem_cache_op) +#endif + #endif /* __TBM_BUFMGR_TGL_H__ */ -- 2.7.4