From a8d0414ebf373625ba1ae0268506a2b7c2d621f1 Mon Sep 17 00:00:00 2001 From: Ruixuan Li Date: Mon, 26 Nov 2018 20:53:39 +0800 Subject: [PATCH] emmc: modify cophase for tl1 [1/1] PD#172587 Problem: emmc data crc error Solution: modify cophase under kernel for tl1 Verify: test pass on skt Change-Id: Id4997ef2288a53e6f401744664aaf6b05cf36e38 Signed-off-by: Ruixuan Li --- arch/arm/boot/dts/amlogic/tl1_t962x2_skt.dts | 18 ++++++++++++++++++ arch/arm/boot/dts/amlogic/tl1_t962x2_x301.dts | 18 ++++++++++++++++++ drivers/amlogic/mmc/aml_sd_emmc.c | 2 +- drivers/amlogic/mmc/aml_sd_emmc_v3.c | 18 +++++++++++++++--- 4 files changed, 52 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/amlogic/tl1_t962x2_skt.dts b/arch/arm/boot/dts/amlogic/tl1_t962x2_skt.dts index 42edae1d..be80c17 100644 --- a/arch/arm/boot/dts/amlogic/tl1_t962x2_skt.dts +++ b/arch/arm/boot/dts/amlogic/tl1_t962x2_skt.dts @@ -1120,6 +1120,24 @@ }; }; /* end of pinctrl_aobus */ +&sd_emmc_c { + status = "okay"; + emmc { + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + /* "MMC_CAP_1_8V_DDR", */ + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200"; + /* "MMC_CAP2_HS400";*/ + f_min = <400000>; + f_max = <200000000>; + }; +}; + &sd_emmc_b { status = "okay"; sd { diff --git a/arch/arm/boot/dts/amlogic/tl1_t962x2_x301.dts b/arch/arm/boot/dts/amlogic/tl1_t962x2_x301.dts index 3402f2d..144772a 100644 --- a/arch/arm/boot/dts/amlogic/tl1_t962x2_x301.dts +++ b/arch/arm/boot/dts/amlogic/tl1_t962x2_x301.dts @@ -1120,6 +1120,24 @@ }; }; /* end of pinctrl_aobus */ +&sd_emmc_c { + status = "okay"; + emmc { + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + /* "MMC_CAP_1_8V_DDR", */ + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200"; + /* "MMC_CAP2_HS400";*/ + f_min = <400000>; + f_max = <200000000>; + }; +}; + &sd_emmc_b { status = "okay"; sd { diff --git a/drivers/amlogic/mmc/aml_sd_emmc.c b/drivers/amlogic/mmc/aml_sd_emmc.c index 5145c91..da47ccc0 100644 --- a/drivers/amlogic/mmc/aml_sd_emmc.c +++ b/drivers/amlogic/mmc/aml_sd_emmc.c @@ -3596,7 +3596,7 @@ static struct meson_mmc_data mmc_data_tl1 = { .sdmmc.init.core_phase = 3, .sdmmc.init.tx_phase = 0, .sdmmc.init.rx_phase = 0, - .sdmmc.hs.core_phase = 1, + .sdmmc.hs.core_phase = 3, .sdmmc.ddr.core_phase = 2, .sdmmc.hs2.core_phase = 3, .sdmmc.hs4.tx_delay = 0, diff --git a/drivers/amlogic/mmc/aml_sd_emmc_v3.c b/drivers/amlogic/mmc/aml_sd_emmc_v3.c index 4e5112f..806d389 100644 --- a/drivers/amlogic/mmc/aml_sd_emmc_v3.c +++ b/drivers/amlogic/mmc/aml_sd_emmc_v3.c @@ -116,6 +116,7 @@ int meson_mmc_clk_init_v3(struct amlsd_host *host) u32 vconf = 0; struct sd_emmc_config *pconf = (struct sd_emmc_config *)&vconf; struct mmc_phase *init = &(host->data->sdmmc.init); + struct mmc_phase *calc = &(host->data->sdmmc.calc); writel(0, host->base + SD_EMMC_ADJUST_V3); writel(0, host->base + SD_EMMC_DELAY1_V3); @@ -133,6 +134,11 @@ int meson_mmc_clk_init_v3(struct amlsd_host *host) pclkc->core_phase = init->core_phase; /* 2: 180 phase */ pclkc->rx_phase = init->rx_phase; pclkc->tx_phase = init->tx_phase; + if ((host->data->chip_type >= MMC_CHIP_G12A) + && (host->data->chip_type != MMC_CHIP_TL1)) { + pclkc->core_phase = calc->core_phase; + pclkc->tx_phase = calc->tx_phase; + } pclkc->always_on = 1; /* Keep clock always on */ writel(vclkc, host->base + SD_EMMC_CLOCK_V3); @@ -333,7 +339,9 @@ static void aml_sd_emmc_set_timing_v3(struct amlsd_platform *pdata, /* overide co-phase by dts */ if (pdata->co_phase) clkc->core_phase = pdata->co_phase; - if (pdata->calc_f) { + if ((pdata->calc_f) + && ((host->data->chip_type >= MMC_CHIP_G12A) + && (host->data->chip_type != MMC_CHIP_TL1))) { clkc->core_phase = para->calc.core_phase; clkc->tx_phase = para->calc.tx_phase; } @@ -343,7 +351,9 @@ static void aml_sd_emmc_set_timing_v3(struct amlsd_platform *pdata, } else if (timing == MMC_TIMING_SD_HS) { if (aml_card_type_non_sdio(pdata)) clkc->core_phase = para->sd_hs.core_phase; - if (pdata->calc_f) { + if ((pdata->calc_f) + && ((host->data->chip_type >= MMC_CHIP_G12A) + && (host->data->chip_type != MMC_CHIP_TL1))) { clkc->core_phase = para->calc.core_phase; clkc->tx_phase = para->calc.tx_phase; } @@ -359,7 +369,9 @@ static void aml_sd_emmc_set_timing_v3(struct amlsd_platform *pdata, } } - if (pdata->calc_f) { + if ((pdata->calc_f) + && ((host->data->chip_type >= MMC_CHIP_G12A) + && (host->data->chip_type != MMC_CHIP_TL1))) { if (timing <= MMC_TIMING_SD_HS) { ret = aml_fixdiv_calc(&fixdiv, &pdata->clk_lay); if (!ret) { -- 2.7.4