From a819f6c8d1f4909a1ac3a2eff390236e4e31dba3 Mon Sep 17 00:00:00 2001 From: Philip Reames Date: Mon, 31 Oct 2022 13:34:28 -0700 Subject: [PATCH] [InstCombine] Allow simplify demanded transformations on scalable vectors Differential Revision: https://reviews.llvm.org/D136475 --- llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp | 7 +++---- llvm/test/Transforms/InstCombine/mul-masked-bits.ll | 3 +-- llvm/test/Transforms/InstCombine/udiv-simplify.ll | 3 +-- 3 files changed, 5 insertions(+), 8 deletions(-) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp index 6fdafbf..3276c9a 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp @@ -130,9 +130,6 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask, if (Depth == MaxAnalysisRecursionDepth) return nullptr; - if (isa(VTy)) - return nullptr; - Instruction *I = dyn_cast(V); if (!I) { computeKnownBits(V, Known, Depth, CxtI); @@ -424,7 +421,9 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask, if (auto *DstVTy = dyn_cast(VTy)) { if (auto *SrcVTy = dyn_cast(I->getOperand(0)->getType())) { - if (cast(DstVTy)->getNumElements() != + if (isa(DstVTy) || + isa(SrcVTy) || + cast(DstVTy)->getNumElements() != cast(SrcVTy)->getNumElements()) // Don't touch a bitcast between vectors of different element counts. return nullptr; diff --git a/llvm/test/Transforms/InstCombine/mul-masked-bits.ll b/llvm/test/Transforms/InstCombine/mul-masked-bits.ll index 9122bf0..74e9620 100644 --- a/llvm/test/Transforms/InstCombine/mul-masked-bits.ll +++ b/llvm/test/Transforms/InstCombine/mul-masked-bits.ll @@ -82,8 +82,7 @@ define @combine_mul_self_demandedbits_vector2( [[X:%.*]] ; CHECK-NEXT: [[TMP2:%.*]] = mul [[TMP1]], [[TMP1]] -; CHECK-NEXT: [[TMP3:%.*]] = and [[TMP2]], shufflevector ( insertelement ( poison, i32 -3, i32 0), poison, zeroinitializer) -; CHECK-NEXT: ret [[TMP3]] +; CHECK-NEXT: ret [[TMP2]] ; %1 = freeze %x %2 = mul %1, %1 diff --git a/llvm/test/Transforms/InstCombine/udiv-simplify.ll b/llvm/test/Transforms/InstCombine/udiv-simplify.ll index 9e5b02f..de00e89 100644 --- a/llvm/test/Transforms/InstCombine/udiv-simplify.ll +++ b/llvm/test/Transforms/InstCombine/udiv-simplify.ll @@ -106,8 +106,7 @@ define i32 @udiv_exact_demanded(i32 %a) { define @udiv_demanded3( %a) { ; CHECK-LABEL: @udiv_demanded3( -; CHECK-NEXT: [[O:%.*]] = or [[A:%.*]], shufflevector ( insertelement ( poison, i32 3, i32 0), poison, zeroinitializer) -; CHECK-NEXT: [[U:%.*]] = udiv [[O]], shufflevector ( insertelement ( poison, i32 12, i32 0), poison, zeroinitializer) +; CHECK-NEXT: [[U:%.*]] = udiv [[A:%.*]], shufflevector ( insertelement ( poison, i32 12, i32 0), poison, zeroinitializer) ; CHECK-NEXT: ret [[U]] ; %o = or %a, shufflevector ( insertelement ( poison, i32 3, i32 0), poison, zeroinitializer) -- 2.7.4