From a8108f1d4440fc72c51eb687d5c422ac6500bf20 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Wed, 18 Jan 2023 02:50:32 -0800 Subject: [PATCH] anv: Add missing untyped data port flush on PIPELINE_SELECT MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit See the comments in emit_apply_pipe_flushes(). Flushing HDC is not sufficient in GPGPU mode, and we need to set the untyped data port flush bit as well. Fixes many dEQP-VK failures with INTEL_COMPUTE_CLASS=1 on Alchemist. Fixes: 1067ec90a59 ("anv: Update PIPELINE_CONTROL flush when switching pipeline mode in TGL+") Reviewed-by: Lionel Landwerlin Reviewed-by: José Roberto de Souza Part-of: --- src/intel/vulkan/genX_cmd_buffer.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index a584841..eda096b 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -6436,6 +6436,8 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer, if (cmd_buffer->state.current_pipeline == _3D) { bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_DEPTH_CACHE_FLUSH_BIT; + } else { + bits |= ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT; } anv_add_pending_pipe_bits(cmd_buffer, bits, "flush PIPELINE_SELECT"); #else -- 2.7.4