From a7ffb8154d698cdcf5cad3f859f2cd7efb73ae82 Mon Sep 17 00:00:00 2001 From: Lucas De Marchi Date: Fri, 29 Jan 2021 10:29:39 -0800 Subject: [PATCH] drm/i915/adl_s: Add power wells MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit TGL power wells can be re-used for ADL-S with the exception of the fake power well for TC_COLD, just like DG-1. BSpec: 53597 Bspec: 49231 Cc: Imre Deak Cc: Matt Roper Cc: Aditya Swarup Signed-off-by: Lucas De Marchi Signed-off-by: Aditya Swarup Reviewed-by: Matt Roper Signed-off-by: José Roberto de Souza Link: https://patchwork.freedesktop.org/patch/msgid/20210129182945.217078-3-aditya.swarup@intel.com --- drivers/gpu/drm/i915/display/intel_display_power.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index bb04b50..2f35a21 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -4689,7 +4689,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) * The enabling order will be from lower to higher indexed wells, * the disabling order is reversed. */ - if (IS_DG1(dev_priv)) { + if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) { err = set_power_wells_mask(power_domains, tgl_power_wells, BIT_ULL(TGL_DISP_PW_TC_COLD_OFF)); } else if (IS_ROCKETLAKE(dev_priv)) { -- 2.7.4