From a78dd726f46de63529585b2569314d35ce39105d Mon Sep 17 00:00:00 2001 From: Luke Date: Wed, 1 Sep 2021 13:08:13 +0800 Subject: [PATCH] [SLP][RISCV] Implement unsigned getMinVectorRegisterBitWidth() for RISCV Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D108973 --- llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h index 4853351..b1d0e38 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h +++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h @@ -73,6 +73,10 @@ public: llvm_unreachable("Unsupported register kind"); } + unsigned getMinVectorRegisterBitWidth() const { + return ST->hasStdExtV() ? ST->getMinRVVVectorSizeInBits() : 0; + } + InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, -- 2.7.4