From a75631c2e32c8b4d51cb9806f90f6c6bfcf5834d Mon Sep 17 00:00:00 2001 From: Han Gao Date: Sun, 23 Jul 2023 16:28:03 +0800 Subject: [PATCH] fix: unknown CSR 'mhcr' (arch/riscv/cpu/c9xx/cpu.c) Signed-off-by: Han Gao --- arch/riscv/cpu/c9xx/cpu.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/riscv/cpu/c9xx/cpu.c b/arch/riscv/cpu/c9xx/cpu.c index ba370cfb..8cb403ab 100644 --- a/arch/riscv/cpu/c9xx/cpu.c +++ b/arch/riscv/cpu/c9xx/cpu.c @@ -125,10 +125,11 @@ void icache_enable(void) #ifdef CONFIG_SPL_BUILD #ifdef CONFIG_SPL_RISCV_MMODE #ifdef CONFIG_TARGET_LIGHT_C910 +// mhcr is 0x7c1 asm volatile ( - "csrr x29, mhcr\n\t" + "csrr x29, 0x7c1\n\t" "ori x28, x29, 0x1\n\t" - "csrw mhcr, x28\n\t" + "csrw 0x7c1, x28\n\t" ); #endif #endif @@ -142,7 +143,7 @@ void dcache_enable(void) #ifdef CONFIG_TARGET_LIGHT_C910 asm volatile ( "li x29, 0x11ff\n\t" - "csrw mhcr, x29\n\t" + "csrw 0x7c1, x29\n\t" ); #endif #endif -- 2.34.1