From a74b33f61251030644c70c8dc11daab4aca5a1f0 Mon Sep 17 00:00:00 2001 From: David Stuttard Date: Thu, 5 Mar 2020 14:09:27 +0000 Subject: [PATCH] AMDGPU: Fix SMRD test in trivially disjoint mem access code Summary: This seems like an obvious error - cut and paste issue? The change does make a change to one of the lit tests - it stops s_buffer_load re-ordering past an MUBUF instruction (which is not surprising). Change-Id: I80be99de5b62af4f42e91af2591b76a52ac9efa6 Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, hiraditya, kerbowa, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D75686 --- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 2 +- llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 85c9bc8..2e0b78b 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -2666,7 +2666,7 @@ bool SIInstrInfo::areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, if (isSMRD(MIb)) return checkInstOffsetsDoNotOverlap(MIa, MIb); - return !isFLAT(MIb) && !isMUBUF(MIa) && !isMTBUF(MIa); + return !isFLAT(MIb) && !isMUBUF(MIb) && !isMTBUF(MIb); } if (isFLAT(MIa)) { diff --git a/llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll b/llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll index adecea8..ec2dbb9 100644 --- a/llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll +++ b/llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll @@ -88,10 +88,10 @@ define amdgpu_kernel void @no_reorder_barrier_local_load_global_store_local_load ; GCN-LABEL: {{^}}reorder_constant_load_global_store_constant_load: ; GCN-DAG: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}} ; GCN: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}} -; CI: buffer_store_dword -; CI-DAG: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x1 -; CI-DAG: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x3 +; CI: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x1 +; CI: buffer_store_dword +; CI: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x3 ; GFX9: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x4 ; GFX9: global_store_dword -- 2.7.4