From a6e562fe36b2bae780589a81a11fceb6e1b4a9f7 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Stefan=20M=C3=A4tje?= Date: Tue, 30 Nov 2021 01:06:56 +0100 Subject: [PATCH] Fix wrong QSPI clock calculation for AM4372 MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit On AM4372 the SPI_GCLK input gets its clock from the PRCM module which divides the PER_CLKOUTM2 frequency (192MHz) by a fixed factor of 4. See AM437x Reference Manual in section 27 QSPI >> 27.2 Integration. The QSPI_FCLK therefore needs to take this factor into account and becomes (192000000 / 4). Signed-off-by: Stefan Mätje --- drivers/spi/ti_qspi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index c542f40..99acb10 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -30,7 +30,8 @@ DECLARE_GLOBAL_DATA_PTR; /* ti qpsi register bit masks */ #define QSPI_TIMEOUT 2000000 -#define QSPI_FCLK 192000000 +/* AM4372: QSPI gets SPI_GCLK from PRCM unit as PER_CLKOUTM2 divided by 4. */ +#define QSPI_FCLK (192000000 / 4) #define QSPI_DRA7XX_FCLK 76800000 #define QSPI_WLEN_MAX_BITS 128 #define QSPI_WLEN_MAX_BYTES (QSPI_WLEN_MAX_BITS >> 3) -- 2.7.4