From a6d41b925b3b545b4c3ed95abb14895e4e0ef271 Mon Sep 17 00:00:00 2001 From: Jian Hu Date: Mon, 26 Nov 2018 15:28:21 +0800 Subject: [PATCH] clk: tm2: add dsu clock [2/3] PD#SWPL-6758 Problem: tm2 dsu clock does not work Solution: 1.add dsu clock 2.gp1 pll clock Verify: verify on tm2 ad311 Change-Id: I8090a75d15ae4e532f6ae04563d6d0158f8fbc87 Signed-off-by: Jian Hu --- drivers/amlogic/clk/tl1/tl1.c | 196 +++++++++++++++++++++++++-- drivers/amlogic/clk/tl1/tl1.h | 6 +- drivers/amlogic/clk/tl1/tl1_clk-pll.c | 4 +- include/dt-bindings/clock/amlogic,tl1-clkc.h | 79 +++++------ 4 files changed, 236 insertions(+), 49 deletions(-) diff --git a/drivers/amlogic/clk/tl1/tl1.c b/drivers/amlogic/clk/tl1/tl1.c index c9d660c..44bbe1e 100644 --- a/drivers/amlogic/clk/tl1/tl1.c +++ b/drivers/amlogic/clk/tl1/tl1.c @@ -14,7 +14,6 @@ * more details. * */ - #include #include #include @@ -107,13 +106,13 @@ static struct meson_clk_pll tl1_gp1_pll = { }, .n = { .reg_off = HHI_GP1_PLL_CNTL0, - .shift = 9, + .shift = 10, .width = 5, }, .od = { .reg_off = HHI_GP1_PLL_CNTL0, .shift = 16, - .width = 2, + .width = 3, }, .rate_table = tl1_pll_rate_table, .rate_count = ARRAY_SIZE(tl1_pll_rate_table), @@ -402,7 +401,7 @@ static struct meson_clk_mpll tl1_mpll3 = { * post-dividers and should be modelled with their respective PLLs via the * forthcoming coordinated clock rates feature */ -static u32 mux_table_cpu_p[] = { 0, 1, 2 }; +static u32 mux_table_cpu_p[] = { 0, 1, 2, 3 }; static u32 mux_table_cpu_px[] = { 0, 1 }; static struct meson_cpu_mux_divider tl1_cpu_fclk_p = { .reg = (void *)HHI_SYS_CPU_CLK_CNTL0, @@ -447,8 +446,8 @@ static struct meson_cpu_mux_divider tl1_cpu_fclk_p = { .name = "cpu_fixedpll_p", .ops = &meson_fclk_cpu_ops, .parent_names = (const char *[]){ "xtal", "fclk_div2", - "fclk_div3"}, - .num_parents = 3, + "fclk_div3", "gp1_pll"}, + .num_parents = 4, .flags = (CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED), }, }; @@ -470,6 +469,143 @@ static struct meson_clk_cpu tl1_cpu_clk = { }, }; + +/* dsu clocks */ +static const char * const dsu_fixed_source_sel_parent_names[] = { + "xtal", "fclk_div2", "fclk_div3", "gp1_pll" +}; + +/* fixed sel0 */ +static struct clk_mux tl1_dsu_fixed_source_sel0 = { + .reg = (void *)HHI_SYS_CPU_CLK_CNTL5, + .mask = 0x3, + .shift = 0, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "dsu_fixed_source_sel0", + .ops = &clk_mux_ops, + .parent_names = dsu_fixed_source_sel_parent_names, + .num_parents = ARRAY_SIZE(dsu_fixed_source_sel_parent_names), + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_divider tl1_dsu_fixed_source_div0 = { + .reg = (void *)HHI_SYS_CPU_CLK_CNTL5, + .shift = 4, + .width = 6, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "dsu_fixed_source_div0", + .ops = &clk_divider_ops, + .parent_names = (const char *[]){ "dsu_fixed_source_sel0" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_mux tl1_dsu_fixed_sel0 = { + .reg = (void *)HHI_SYS_CPU_CLK_CNTL5, + .mask = 0x1, + .shift = 2, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "dsu_fixed_sel0", + .ops = &clk_mux_ops, + .parent_names = (const char *[]){ "dsu_fixed_source_sel0", + "dsu_fixed_source_div0" }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + }, +}; + +/* fixed sel1 */ +static struct clk_mux tl1_dsu_fixed_source_sel1 = { + .reg = (void *)HHI_SYS_CPU_CLK_CNTL5, + .mask = 0x3, + .shift = 16, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "dsu_fixed_source_sel1", + .ops = &clk_mux_ops, + .parent_names = dsu_fixed_source_sel_parent_names, + .num_parents = ARRAY_SIZE(dsu_fixed_source_sel_parent_names), + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_divider tl1_dsu_fixed_source_div1 = { + .reg = (void *)HHI_SYS_CPU_CLK_CNTL5, + .shift = 20, + .width = 6, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "dsu_fixed_source_div1", + .ops = &clk_divider_ops, + .parent_names = (const char *[]){ "dsu_fixed_source_sel1" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_mux tl1_dsu_fixed_sel1 = { + .reg = (void *)HHI_SYS_CPU_CLK_CNTL5, + .mask = 0x1, + .shift = 18, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "dsu_fixed_sel1", + .ops = &clk_mux_ops, + .parent_names = (const char *[]){ "dsu_fixed_source_sel1", + "dsu_fixed_source_div1" }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + }, +}; + +/* dsu pre clock parent 0 */ +static struct clk_mux tl1_dsu_pre0_clk = { + .reg = (void *)HHI_SYS_CPU_CLK_CNTL5, + .mask = 0x1, + .shift = 10, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "dsu_pre0_clk", + .ops = &clk_mux_ops, + .parent_names = (const char *[]){ "dsu_fixed_sel0", + "dsu_fixed_sel1" }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + }, +}; + +static struct clk_mux tl1_dsu_pre_clk = { + .reg = (void *)HHI_SYS_CPU_CLK_CNTL5, + .mask = 0x1, + .shift = 11, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "dsu_pre_clk", + .ops = &clk_mux_ops, + .parent_names = (const char *[]){ "dsu_pre0_clk", "sys_pll" }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + }, +}; + +static struct clk_mux tl1_dsu_clk = { + .reg = (void *)HHI_SYS_CPU_CLK_CNTL6, + .mask = 0x1, + .shift = 27, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "dsu_clk", + .ops = &clk_mux_ops, + .parent_names = (const char *[]){ "cpu_clk", "dsu_pre_clk" }, + .num_parents = 2, + }, +}; + static u32 mux_table_clk81[] = { 6, 5, 7 }; static struct clk_mux tl1_mpeg_clk_sel = { @@ -718,6 +854,15 @@ static struct clk_hw *tl1_clk_hws[] = { [CLKID_CPU_FCLK_P] = &tl1_cpu_fclk_p.hw, [CLKID_CPU_CLK] = &tl1_cpu_clk.mux.hw, + [CLKID_DSU_SOURCE_SEL0] = &tl1_dsu_fixed_source_sel0.hw, + [CLKID_DSU_SOURCE_DIV0] = &tl1_dsu_fixed_source_div0.hw, + [CLKID_DSU_SEL0] = &tl1_dsu_fixed_sel0.hw, + [CLKID_DSU_SOURCE_SEL1] = &tl1_dsu_fixed_source_sel1.hw, + [CLKID_DSU_SOURCE_DIV1] = &tl1_dsu_fixed_source_div1.hw, + [CLKID_DSU_SEL1] = &tl1_dsu_fixed_sel1.hw, + [CLKID_DSU_PRE_PARENT0] = &tl1_dsu_pre0_clk.hw, + [CLKID_DSU_PRE_CLK] = &tl1_dsu_pre_clk.hw, + [CLKID_DSU_CLK] = &tl1_dsu_clk.hw, }; /* Convenience tables to populate base addresses in .probe */ @@ -847,6 +992,28 @@ static void __init tl1_clkc_init(struct device_node *np) tl1_cpu_clk.mux.reg = clk_base + (unsigned long)tl1_cpu_clk.mux.reg; + /* Populate the base address for DSU clk */ + tl1_dsu_fixed_source_sel0.reg = clk_base + + (unsigned long)tl1_dsu_fixed_source_sel0.reg; + tl1_dsu_fixed_source_div0.reg = clk_base + + (unsigned long)tl1_dsu_fixed_source_div0.reg; + tl1_dsu_fixed_sel0.reg = clk_base + + (unsigned long)tl1_dsu_fixed_sel0.reg; + + tl1_dsu_fixed_source_sel1.reg = clk_base + + (unsigned long)tl1_dsu_fixed_source_sel1.reg; + tl1_dsu_fixed_source_div1.reg = clk_base + + (unsigned long)tl1_dsu_fixed_source_div1.reg; + tl1_dsu_fixed_sel1.reg = clk_base + + (unsigned long)tl1_dsu_fixed_sel1.reg; + + tl1_dsu_pre0_clk.reg = clk_base + + (unsigned long)tl1_dsu_pre0_clk.reg; + tl1_dsu_pre_clk.reg = clk_base + + (unsigned long)tl1_dsu_pre_clk.reg; + tl1_dsu_clk.reg = clk_base + + (unsigned long)tl1_dsu_clk.reg; + /* Populate base address for gates */ for (i = 0; i < ARRAY_SIZE(tl1_clk_gates); i++) tl1_clk_gates[i]->reg = clk_base + @@ -869,8 +1036,8 @@ static void __init tl1_clkc_init(struct device_node *np) /*register all clks*/ for (clkid = 0; clkid < CLOCK_GATE; clkid++) { if (tl1_clk_hws[clkid]) { - clks[clkid] = clk_register(NULL, tl1_clk_hws[clkid]); - WARN_ON(IS_ERR(clks[clkid])); + clks[clkid] = clk_register(NULL, tl1_clk_hws[clkid]); + WARN_ON(IS_ERR(clks[clkid])); } } @@ -879,6 +1046,9 @@ static void __init tl1_clkc_init(struct device_node *np) meson_tl1_gpu_init(); meson_tl1_misc_init(); + /* now cpu clock parent is sys pll , that is to say register + * sys pll notify clock, why not register tl1_sys_pll.hw derectly? + */ parent_hw = clk_hw_get_parent(&tl1_cpu_clk.mux.hw); parent_clk = parent_hw->clk; ret = clk_notifier_register(parent_clk, &tl1_cpu_clk.clk_nb); @@ -888,6 +1058,16 @@ static void __init tl1_clkc_init(struct device_node *np) goto iounmap; } + /* set sys pll as dsu_pre's parent*/ + /*clk_set_parent(tl1_dsu_pre_clk.hw.clk, tl1_sys_pll.hw.clk);*/ + /* set tl1_dsu_pre0_clk to 1.5G, gp1 pll is 1.5G */ + /*clk_set_rate(tl1_dsu_pre0_clk.hw.clk, 1500000000);*/ + /*set tl1_dsu_pre0_clk as dsu_pre's parent */ + /*clk_set_parent(tl1_dsu_pre_clk.hw.clk, tl1_dsu_pre0_clk.hw.clk);*/ + /*set dsu pre clk to 1GHZ*/ + clk_set_rate(tl1_dsu_pre_clk.hw.clk, 1000000000); + clk_prepare_enable(tl1_dsu_pre_clk.hw.clk); + ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); if (ret < 0) { diff --git a/drivers/amlogic/clk/tl1/tl1.h b/drivers/amlogic/clk/tl1/tl1.h index 94e9608..8a75d8c 100644 --- a/drivers/amlogic/clk/tl1/tl1.h +++ b/drivers/amlogic/clk/tl1/tl1.h @@ -56,7 +56,7 @@ #define HHI_GCLK_OTHER 0xd0 /* 0x34 offset in datasheet */ #define HHI_GCLK_AO 0x154 /* 0x55 offset in datasheet */ - +#define HHI_SYS_CPU_CLK_CNTL1 0x15C /* 0x57 offset in datasheet1 */ #define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in datasheet */ #define HHI_SPICC_HCLK_CNTL 0x168 /* 0x5a offset in datasheet */ @@ -70,7 +70,7 @@ #define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in datasheet */ #define HHI_VPU_CLKC_CNTL 0x1b4 /* 0x6d offset in datasheet1 */ #define HHI_VPU_CLK_CNTL 0x1bC /* 0x6f offset in datasheet1 */ -#define HHI_AUDPLL_CLK_OUT_CNTL 0x1E0 /* 0x74 offset in datasheet1 */ +#define HHI_AUDPLL_CLK_OUT_CNTL 0x1E0 /* 0x74 offset in datasheet1 */ #define HHI_VDEC_CLK_CNTL 0x1E0 /* 0x78 offset in datasheet1 */ #define HHI_VDEC2_CLK_CNTL 0x1E4 /* 0x79 offset in datasheet1 */ #define HHI_VDEC3_CLK_CNTL 0x1E8 /* 0x7a offset in datasheet1 */ @@ -80,6 +80,8 @@ #define HHI_HDMIRX_CLK_CNTL 0x200 /* 0x80 offset in datasheet1 */ #define HHI_HDMIRX_AUD_CLK_CNTL 0x204 /* 0x81 offset in datasheet1 */ #define HHI_VPU_CLKB_CNTL 0x20C /* 0x83 offset in datasheet1 */ +#define HHI_SYS_CPU_CLK_CNTL5 0x21C /* 0x87 offset in datasheet1 */ +#define HHI_SYS_CPU_CLK_CNTL6 0x220 /* 0x88 offset in datasheet1 */ #define HHI_HDMIRX_METER_CLK_CNTL 0x234 /* 0x8d offset in datasheet1 */ #define HHI_VDIN_MEAS_CLK_CNTL 0x250 /* 0x94 offset in datasheet1 */ diff --git a/drivers/amlogic/clk/tl1/tl1_clk-pll.c b/drivers/amlogic/clk/tl1/tl1_clk-pll.c index d724809..c2b530d 100644 --- a/drivers/amlogic/clk/tl1/tl1_clk-pll.c +++ b/drivers/amlogic/clk/tl1/tl1_clk-pll.c @@ -266,7 +266,8 @@ static int meson_tl1_pll_set_rate(struct clk_hw *hw, unsigned long rate, writel(TL1_PLL_CNTL6, cntlbase + (unsigned long)(6*4)); udelay(10); - } else if (!strcmp(clk_hw_get_name(hw), "gp0_pll")) { + } else if (!strcmp(clk_hw_get_name(hw), "gp0_pll") || + !strcmp(clk_hw_get_name(hw), "gp1_pll")) { writel((readl(cntlbase) | MESON_PLL_RESET) & (~MESON_PLL_ENABLE), cntlbase); writel(TL1_GP0_PLL_CNTL1, @@ -419,6 +420,7 @@ static int meson_tl1_pll_enable(struct clk_hw *hw) } if (!strcmp(clk_hw_get_name(hw), "gp0_pll") + || !strcmp(clk_hw_get_name(hw), "gp1_pll") || !strcmp(clk_hw_get_name(hw), "hifi_pll") || !strcmp(clk_hw_get_name(hw), "sys_pll")) { void *cntlbase = pll->base + p->reg_off; diff --git a/include/dt-bindings/clock/amlogic,tl1-clkc.h b/include/dt-bindings/clock/amlogic,tl1-clkc.h index 7e4f174..733d470 100644 --- a/include/dt-bindings/clock/amlogic,tl1-clkc.h +++ b/include/dt-bindings/clock/amlogic,tl1-clkc.h @@ -39,47 +39,50 @@ #define CLKID_MPLL1 15 #define CLKID_MPLL2 16 #define CLKID_MPLL3 17 -#define CLKID_CPU_FCLK_P00 18 -#define CLKID_CPU_FCLK_P01 19 -#define CLKID_CPU_FCLK_P0 20 -#define CLKID_CPU_FCLK_P10 21 -#define CLKID_CPU_FCLK_P11 22 -#define CLKID_CPU_FCLK_P1 23 -#define CLKID_CPU_FCLK_P 24 -#define CLKID_CPU_CLK 25 +#define CLKID_CPU_FCLK_P 18 +#define CLKID_CPU_CLK 19 +#define CLKID_DSU_SOURCE_SEL0 20 +#define CLKID_DSU_SOURCE_DIV0 21 +#define CLKID_DSU_SEL0 22 +#define CLKID_DSU_SOURCE_SEL1 23 +#define CLKID_DSU_SOURCE_DIV1 24 +#define CLKID_DSU_SEL1 25 +#define CLKID_DSU_PRE_PARENT0 26 +#define CLKID_DSU_PRE_CLK 27 +#define CLKID_DSU_CLK 28 /*#define CLKID_ADC_PLL 24*/ -#define CLKID_PCIE_PLL 26 -#define CLKID_VIPNANOQ 27 -#define CLKID_PCIE1 28 -#define CLKID_PCIE0PHY 29 -#define CLKID_PCIE1PHY 30 -#define CLKID_PARSER1 31 -#define CLKID_HDCP22_PCLK 32 -#define CLKID_HDMITX_PCLK 33 -#define CLKID_HDMITX_AXI_PCLK 34 -#define CLKID_DSPB 35 -#define CLKID_DSPA 36 +#define CLKID_PCIE_PLL 29 +#define CLKID_VIPNANOQ 30 +#define CLKID_PCIE1 31 +#define CLKID_PCIE0PHY 32 +#define CLKID_PCIE1PHY 33 +#define CLKID_PARSER1 34 +#define CLKID_HDCP22_PCLK 35 +#define CLKID_HDMITX_PCLK 36 +#define CLKID_HDMITX_AXI_PCLK 37 +#define CLKID_DSPB 38 +#define CLKID_DSPA 39 /* dsp clocks */ -#define CLKID_DSPA_MUX_A 37 -#define CLKID_DSPA_DIV_A 38 -#define CLKID_DSPA_GATE_A 39 -#define CLKID_DSPA_MUX_B 40 -#define CLKID_DSPA_DIV_B 41 -#define CLKID_DSPA_GATE_B 42 -#define CLKID_DSPA_MUX 43 -#define CLKID_DSPB_MUX_A 44 -#define CLKID_DSPB_DIV_A 45 -#define CLKID_DSPB_GATE_A 46 -#define CLKID_DSPB_MUX_B 47 -#define CLKID_DSPB_DIV_B 48 -#define CLKID_DSPB_GATE_B 49 -#define CLKID_DSPB_MUX 50 -#define CLKID_PCIE0_GATE 51 -#define CLKID_PCIE1_GATE 52 -#define CLKID_PCIE0 53 -#define CLKID_PCIE01_ENABLE 54 +#define CLKID_DSPA_MUX_A 40 +#define CLKID_DSPA_DIV_A 41 +#define CLKID_DSPA_GATE_A 42 +#define CLKID_DSPA_MUX_B 43 +#define CLKID_DSPA_DIV_B 44 +#define CLKID_DSPA_GATE_B 45 +#define CLKID_DSPA_MUX 46 +#define CLKID_DSPB_MUX_A 47 +#define CLKID_DSPB_DIV_A 48 +#define CLKID_DSPB_GATE_A 49 +#define CLKID_DSPB_MUX_B 50 +#define CLKID_DSPB_DIV_B 51 +#define CLKID_DSPB_GATE_B 52 +#define CLKID_DSPB_MUX 53 +#define CLKID_PCIE0_GATE 54 +#define CLKID_PCIE1_GATE 55 +#define CLKID_PCIE0 56 +#define CLKID_PCIE01_ENABLE 57 /*HHI_GCLK_MPEG0: 0x50*/ -#define GATE_BASE0 55 +#define GATE_BASE0 58 #define CLKID_DDR (GATE_BASE0 + 0) #define CLKID_DOS (GATE_BASE0 + 1) -- 2.7.4