From a6cd4b9bced862533d5ce7ca4dde18d82b623801 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 28 Aug 2018 02:02:29 +0000 Subject: [PATCH] [InstCombine] Extend (add (sext x), cst) --> (sext (add x, cst')) and (add (zext x), cst) --> (zext (add x, cst')) to work for vectors Differential Revision: https://reviews.llvm.org/D51236 llvm-svn: 340796 --- .../Transforms/InstCombine/InstCombineAddSub.cpp | 6 +++-- llvm/test/Transforms/InstCombine/sink-zext.ll | 28 +++++++++++----------- 2 files changed, 18 insertions(+), 16 deletions(-) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp index 58bf5b4..30067fe 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp @@ -1195,7 +1195,8 @@ Instruction *InstCombiner::visitAdd(BinaryOperator &I) { // integer add followed by a sext. if (SExtInst *LHSConv = dyn_cast(LHS)) { // (add (sext x), cst) --> (sext (add x, cst')) - if (ConstantInt *RHSC = dyn_cast(RHS)) { + Constant *RHSC; + if (match(RHS, m_Constant(RHSC))) { if (LHSConv->hasOneUse()) { Constant *CI = ConstantExpr::getTrunc(RHSC, LHSConv->getOperand(0)->getType()); @@ -1231,7 +1232,8 @@ Instruction *InstCombiner::visitAdd(BinaryOperator &I) { // integer add followed by a zext. if (auto *LHSConv = dyn_cast(LHS)) { // (add (zext x), cst) --> (zext (add x, cst')) - if (ConstantInt *RHSC = dyn_cast(RHS)) { + Constant *RHSC; + if (match(RHS, m_Constant(RHSC))) { if (LHSConv->hasOneUse()) { Constant *CI = ConstantExpr::getTrunc(RHSC, LHSConv->getOperand(0)->getType()); diff --git a/llvm/test/Transforms/InstCombine/sink-zext.ll b/llvm/test/Transforms/InstCombine/sink-zext.ll index 2b08608..7180b56 100644 --- a/llvm/test/Transforms/InstCombine/sink-zext.ll +++ b/llvm/test/Transforms/InstCombine/sink-zext.ll @@ -84,8 +84,8 @@ define i64 @test5(i32 %V) { define <2 x i64> @test5_splat(<2 x i32> %V) { ; CHECK-LABEL: @test5_splat( ; CHECK-NEXT: [[ASHR:%.*]] = ashr <2 x i32> [[V:%.*]], -; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i32> [[ASHR]] to <2 x i64> -; CHECK-NEXT: [[ADD:%.*]] = add nsw <2 x i64> [[SEXT]], +; CHECK-NEXT: [[ADDCONV:%.*]] = add nsw <2 x i32> [[ASHR]], +; CHECK-NEXT: [[ADD:%.*]] = sext <2 x i32> [[ADDCONV]] to <2 x i64> ; CHECK-NEXT: ret <2 x i64> [[ADD]] ; %ashr = ashr <2 x i32> %V, @@ -97,8 +97,8 @@ define <2 x i64> @test5_splat(<2 x i32> %V) { define <2 x i64> @test5_vec(<2 x i32> %V) { ; CHECK-LABEL: @test5_vec( ; CHECK-NEXT: [[ASHR:%.*]] = ashr <2 x i32> [[V:%.*]], -; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i32> [[ASHR]] to <2 x i64> -; CHECK-NEXT: [[ADD:%.*]] = add nsw <2 x i64> [[SEXT]], +; CHECK-NEXT: [[ADDCONV:%.*]] = add nsw <2 x i32> [[ASHR]], +; CHECK-NEXT: [[ADD:%.*]] = sext <2 x i32> [[ADDCONV]] to <2 x i64> ; CHECK-NEXT: ret <2 x i64> [[ADD]] ; %ashr = ashr <2 x i32> %V, @@ -123,8 +123,8 @@ define i64 @test6(i32 %V) { define <2 x i64> @test6_splat(<2 x i32> %V) { ; CHECK-LABEL: @test6_splat( ; CHECK-NEXT: [[ASHR:%.*]] = ashr <2 x i32> [[V:%.*]], -; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i32> [[ASHR]] to <2 x i64> -; CHECK-NEXT: [[ADD:%.*]] = add nsw <2 x i64> [[SEXT]], +; CHECK-NEXT: [[ADDCONV:%.*]] = add nsw <2 x i32> [[ASHR]], +; CHECK-NEXT: [[ADD:%.*]] = sext <2 x i32> [[ADDCONV]] to <2 x i64> ; CHECK-NEXT: ret <2 x i64> [[ADD]] ; %ashr = ashr <2 x i32> %V, @@ -136,8 +136,8 @@ define <2 x i64> @test6_splat(<2 x i32> %V) { define <2 x i64> @test6_vec(<2 x i32> %V) { ; CHECK-LABEL: @test6_vec( ; CHECK-NEXT: [[ASHR:%.*]] = ashr <2 x i32> [[V:%.*]], -; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i32> [[ASHR]] to <2 x i64> -; CHECK-NEXT: [[ADD:%.*]] = add nsw <2 x i64> [[SEXT]], +; CHECK-NEXT: [[ADDCONV:%.*]] = add nsw <2 x i32> [[ASHR]], +; CHECK-NEXT: [[ADD:%.*]] = sext <2 x i32> [[ADDCONV]] to <2 x i64> ; CHECK-NEXT: ret <2 x i64> [[ADD]] ; %ashr = ashr <2 x i32> %V, @@ -149,8 +149,8 @@ define <2 x i64> @test6_vec(<2 x i32> %V) { define <2 x i64> @test6_vec2(<2 x i32> %V) { ; CHECK-LABEL: @test6_vec2( ; CHECK-NEXT: [[ASHR:%.*]] = ashr <2 x i32> [[V:%.*]], -; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i32> [[ASHR]] to <2 x i64> -; CHECK-NEXT: [[ADD:%.*]] = add nsw <2 x i64> [[SEXT]], +; CHECK-NEXT: [[ADDCONV:%.*]] = add nsw <2 x i32> [[ASHR]], +; CHECK-NEXT: [[ADD:%.*]] = sext <2 x i32> [[ADDCONV]] to <2 x i64> ; CHECK-NEXT: ret <2 x i64> [[ADD]] ; %ashr = ashr <2 x i32> %V, @@ -175,8 +175,8 @@ define i64 @test7(i32 %V) { define <2 x i64> @test7_splat(<2 x i32> %V) { ; CHECK-LABEL: @test7_splat( ; CHECK-NEXT: [[LSHR:%.*]] = lshr <2 x i32> [[V:%.*]], -; CHECK-NEXT: [[ZEXT:%.*]] = zext <2 x i32> [[LSHR]] to <2 x i64> -; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw <2 x i64> [[ZEXT]], +; CHECK-NEXT: [[ADDCONV:%.*]] = add nuw <2 x i32> [[LSHR]], +; CHECK-NEXT: [[ADD:%.*]] = zext <2 x i32> [[ADDCONV]] to <2 x i64> ; CHECK-NEXT: ret <2 x i64> [[ADD]] ; %lshr = lshr <2 x i32> %V, @@ -188,8 +188,8 @@ define <2 x i64> @test7_splat(<2 x i32> %V) { define <2 x i64> @test7_vec(<2 x i32> %V) { ; CHECK-LABEL: @test7_vec( ; CHECK-NEXT: [[LSHR:%.*]] = lshr <2 x i32> [[V:%.*]], -; CHECK-NEXT: [[ZEXT:%.*]] = zext <2 x i32> [[LSHR]] to <2 x i64> -; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw <2 x i64> [[ZEXT]], +; CHECK-NEXT: [[ADDCONV:%.*]] = add nuw <2 x i32> [[LSHR]], +; CHECK-NEXT: [[ADD:%.*]] = zext <2 x i32> [[ADDCONV]] to <2 x i64> ; CHECK-NEXT: ret <2 x i64> [[ADD]] ; %lshr = lshr <2 x i32> %V, -- 2.7.4