From a6ab0cff08f58de890b48f09fa1ec0f392834aae Mon Sep 17 00:00:00 2001 From: Vitaliy Triang3l Kuzmin Date: Sun, 2 Apr 2023 21:05:53 +0300 Subject: [PATCH] radv: Set DB_Z_INFO.NUM_SAMPLES to MSAA_EXPOSED_SAMPLES without Z/S This case is a new addition in GFX11, and according to PAL, when no depth/stencil attachment is bound, it must be set to the number of coverage samples (the number of SampleMask bits - which is MSAA_EXPOSED_SAMPLES): https://github.com/GPUOpen-Drivers/pal/blob/4640888b579bc9b0951c586b08a4552f71780d0d/src/core/hw/gfxip/gfx9/gfx9UniversalCmdBuffer.cpp#L6978 Without this change, the maximum of depth/stencil and color sample counts is used, and if there are no depth/stencil or color attachments (target- independent rasterization), the Depth Block assumes 1 coverage sample, and thus Primitive Ordered Pixel Shading doesn't work correctly (and fails 4xAA fragment shader interlock CTS tests), and occlusion queries don't count the correct number of samples (according to the "Sample Counting" section of the Vulkan specification, "the occlusion query sample counter increments by one for each sample with a coverage value of 1...") Reviewed-by: Bas Nieuwenhuizen Signed-off-by: Vitaliy Triang3l Kuzmin Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index c14e219..3854083 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -3496,11 +3496,11 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer) } else { unsigned num_samples = 0; - /* On GFX11, DB_Z_INFO.NUM_SAMPLES should always match the framebuffer samples. It affects - * VRS and occlusion queries if depth and stencil are not bound. + /* On GFX11, DB_Z_INFO.NUM_SAMPLES should always match MSAA_EXPOSED_SAMPLES. It affects VRS, + * occlusion queries and Primitive Ordered Pixel Shading if depth and stencil are not bound. */ if (cmd_buffer->device->physical_device->rad_info.gfx_level == GFX11) - num_samples = util_logbase2(render->max_samples); + num_samples = util_logbase2(radv_get_rasterization_samples(cmd_buffer)); if (cmd_buffer->device->physical_device->rad_info.gfx_level == GFX9) radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2); @@ -4356,6 +4356,20 @@ radv_emit_msaa_state(struct radv_cmd_buffer *cmd_buffer) pa_sc_aa_config |= S_028BE0_COVERAGE_TO_SHADER_SELECT(ps->info.ps.reads_fully_covered); + /* On GFX11, DB_Z_INFO.NUM_SAMPLES should always match MSAA_EXPOSED_SAMPLES. It affects VRS, + * occlusion queries and Primitive Ordered Pixel Shading if depth and stencil are not bound. + * This is normally emitted as framebuffer state, but if no attachments are bound the sample + * count is independent of the framebuffer state and hence may need to be updated with MSAA + * state. + * Checking the format, not the image view, because the latter may not exist in a secondary + * command buffer. + */ + if (pdevice->rad_info.gfx_level == GFX11 && render->ds_att.format == VK_FORMAT_UNDEFINED) { + assert(!render->ds_att.iview); + radeon_set_context_reg(cmd_buffer->cs, R_028040_DB_Z_INFO, + S_028040_FORMAT(V_028040_Z_INVALID) | + S_028040_NUM_SAMPLES(log_samples)); + } radeon_set_context_reg(cmd_buffer->cs, R_028804_DB_EQAA, db_eqaa); radeon_set_context_reg(cmd_buffer->cs, R_028BE0_PA_SC_AA_CONFIG, pa_sc_aa_config); radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, -- 2.7.4