From a66b3c3abc4047d774e1a8f19c559f94acfa09ed Mon Sep 17 00:00:00 2001 From: Shunzhou Jiang Date: Mon, 25 Jun 2018 16:58:41 +0800 Subject: [PATCH] clk: clock: meet spicc clk closest and not include 1G PD#164751: clock: fix set spi clock set error Change-Id: I06b9c195441e7b057dbd9bf7d5b864cf8ae44aa1 Signed-off-by: Shunzhou Jiang --- drivers/amlogic/clk/g12a/g12a_clk_misc.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/amlogic/clk/g12a/g12a_clk_misc.c b/drivers/amlogic/clk/g12a/g12a_clk_misc.c index b370b5f..250fc9c 100644 --- a/drivers/amlogic/clk/g12a/g12a_clk_misc.c +++ b/drivers/amlogic/clk/g12a/g12a_clk_misc.c @@ -56,8 +56,8 @@ static struct clk_gate g12a_ts_clk_gate = { }; static const char * const spicc_parent_names[] = { "xtal", - "clk81", "fclk_div4", "fclk_div3", "fclk_div2", "fclk_div5", - "fclk_div7", "gp0_pll"}; + "clk81", "fclk_div4", "fclk_div3", "", "fclk_div5", + "fclk_div7", ""}; /* spicc clk */ static struct clk_mux g12a_spicc0_mux = { @@ -79,6 +79,7 @@ static struct clk_divider g12a_spicc0_div = { .shift = 0, .width = 6, .lock = &clk_lock, + .flags = CLK_DIVIDER_ROUND_CLOSEST, .hw.init = &(struct clk_init_data){ .name = "spicc0_div", .ops = &clk_divider_ops, @@ -120,6 +121,7 @@ static struct clk_divider g12a_spicc1_div = { .shift = 16, .width = 6, .lock = &clk_lock, + .flags = CLK_DIVIDER_ROUND_CLOSEST, .hw.init = &(struct clk_init_data){ .name = "spicc_p1_div", .ops = &clk_divider_ops, -- 2.7.4