From a5d0314b9d5166503e99336bb832b3b81b200399 Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Sun, 30 Oct 2022 08:32:24 +0100 Subject: [PATCH] arm64: dts: qcom: sm6350: Add pinctrl for SDHCI 2 Use the generic pin functions specifically for sdc2. Signed-off-by: Marijn Suijten Acked-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Reviewed-by: Luca Weiss Tested-by: Luca Weiss # sm7225-fairphone-fp4 Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221030073232.22726-3-marijn.suijten@somainline.org --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 44 ++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 2806194..f0e7304 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1074,6 +1074,10 @@ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>; interconnect-names = "sdhc-ddr", "cpu-sdhc"; + pinctrl-0 = <&sdc2_on_state>; + pinctrl-1 = <&sdc2_off_state>; + pinctrl-names = "default", "sleep"; + qcom,dll-config = <0x0007642c>; qcom,ddr-config = <0x80040868>; power-domains = <&rpmhpd SM6350_CX>; @@ -1313,6 +1317,46 @@ #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 157>; + sdc2_off_state: sdc2-off-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + sdc2_on_state: sdc2-on-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <10>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + qup_uart9_default: qup-uart9-default-state { pins = "gpio25", "gpio26"; function = "qup13_f2"; -- 2.7.4