From a573531785f6f01f992b4c68962081925fed5baf Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Tue, 19 Jul 2022 16:44:26 -0700 Subject: [PATCH] intel/compiler/xe2+: Represent dispatch_grf_start_reg in native GRF units. Reviewed-by: Caio Oliveira Part-of: --- src/intel/compiler/brw_fs.cpp | 15 ++++++++++++--- src/intel/compiler/brw_shader.cpp | 4 +++- src/intel/compiler/brw_vec4.cpp | 5 ++++- src/intel/compiler/brw_vec4_gs_visitor.cpp | 6 +++++- src/intel/compiler/brw_vec4_tcs.cpp | 3 ++- src/intel/compiler/brw_vec4_tcs.h | 1 + 6 files changed, 27 insertions(+), 7 deletions(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 0fbbe1e..388ece6 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -7875,7 +7875,10 @@ brw_compile_fs(const struct brw_compiler *compiler, return NULL; } else if (INTEL_SIMD(FS, 8)) { simd8_cfg = v8->cfg; - prog_data->base.dispatch_grf_start_reg = v8->payload().num_regs; + + assert(v8->payload().num_regs % reg_unit(devinfo) == 0); + prog_data->base.dispatch_grf_start_reg = v8->payload().num_regs / reg_unit(devinfo); + prog_data->reg_blocks_8 = brw_register_blocks(v8->grf_used); const performance &perf = v8->performance_analysis.require(); throughput = MAX2(throughput, perf.throughput); @@ -7920,7 +7923,10 @@ brw_compile_fs(const struct brw_compiler *compiler, v16->fail_msg); } else { simd16_cfg = v16->cfg; - prog_data->dispatch_grf_start_reg_16 = v16->payload().num_regs; + + assert(v16->payload().num_regs % reg_unit(devinfo) == 0); + prog_data->dispatch_grf_start_reg_16 = v16->payload().num_regs / reg_unit(devinfo); + prog_data->reg_blocks_16 = brw_register_blocks(v16->grf_used); const performance &perf = v16->performance_analysis.require(); throughput = MAX2(throughput, perf.throughput); @@ -7954,7 +7960,10 @@ brw_compile_fs(const struct brw_compiler *compiler, "SIMD32 shader inefficient\n"); } else { simd32_cfg = v32->cfg; - prog_data->dispatch_grf_start_reg_32 = v32->payload().num_regs; + + assert(v32->payload().num_regs % reg_unit(devinfo) == 0); + prog_data->dispatch_grf_start_reg_32 = v32->payload().num_regs / reg_unit(devinfo); + prog_data->reg_blocks_32 = brw_register_blocks(v32->grf_used); throughput = MAX2(throughput, perf.throughput); } diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp index 0648bdf..e924135 100644 --- a/src/intel/compiler/brw_shader.cpp +++ b/src/intel/compiler/brw_shader.cpp @@ -1396,7 +1396,9 @@ brw_compile_tes(const struct brw_compiler *compiler, return NULL; } - prog_data->base.base.dispatch_grf_start_reg = v.payload().num_regs; + assert(v.payload().num_regs % reg_unit(devinfo) == 0); + prog_data->base.base.dispatch_grf_start_reg = v.payload().num_regs / reg_unit(devinfo); + prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8; fs_generator g(compiler, ¶ms->base, diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp index 2122427..83718f0 100644 --- a/src/intel/compiler/brw_vec4.cpp +++ b/src/intel/compiler/brw_vec4.cpp @@ -23,6 +23,7 @@ #include "brw_vec4.h" #include "brw_fs.h" +#include "brw_eu.h" #include "brw_cfg.h" #include "brw_nir.h" #include "brw_vec4_builder.h" @@ -2643,7 +2644,9 @@ brw_compile_vs(const struct brw_compiler *compiler, return NULL; } - prog_data->base.base.dispatch_grf_start_reg = v.payload().num_regs; + assert(v.payload().num_regs % reg_unit(compiler->devinfo) == 0); + prog_data->base.base.dispatch_grf_start_reg = + v.payload().num_regs / reg_unit(compiler->devinfo); fs_generator g(compiler, ¶ms->base, &prog_data->base.base, v.runtime_check_aads_emit, diff --git a/src/intel/compiler/brw_vec4_gs_visitor.cpp b/src/intel/compiler/brw_vec4_gs_visitor.cpp index 4dbdf78..f4040d6 100644 --- a/src/intel/compiler/brw_vec4_gs_visitor.cpp +++ b/src/intel/compiler/brw_vec4_gs_visitor.cpp @@ -29,6 +29,7 @@ #include "brw_vec4_gs_visitor.h" #include "gfx6_gs_visitor.h" +#include "brw_eu.h" #include "brw_cfg.h" #include "brw_fs.h" #include "brw_nir.h" @@ -822,7 +823,10 @@ brw_compile_gs(const struct brw_compiler *compiler, params->base.stats != NULL, debug_enabled); if (v.run_gs()) { prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8; - prog_data->base.base.dispatch_grf_start_reg = v.payload().num_regs; + + assert(v.payload().num_regs % reg_unit(compiler->devinfo) == 0); + prog_data->base.base.dispatch_grf_start_reg = + v.payload().num_regs / reg_unit(compiler->devinfo); fs_generator g(compiler, ¶ms->base, &prog_data->base.base, false, MESA_SHADER_GEOMETRY); diff --git a/src/intel/compiler/brw_vec4_tcs.cpp b/src/intel/compiler/brw_vec4_tcs.cpp index 0bc3a08..5541460 100644 --- a/src/intel/compiler/brw_vec4_tcs.cpp +++ b/src/intel/compiler/brw_vec4_tcs.cpp @@ -456,7 +456,8 @@ brw_compile_tcs(const struct brw_compiler *compiler, return NULL; } - prog_data->base.base.dispatch_grf_start_reg = v.payload().num_regs; + assert(v.payload().num_regs % reg_unit(devinfo) == 0); + prog_data->base.base.dispatch_grf_start_reg = v.payload().num_regs / reg_unit(devinfo); fs_generator g(compiler, ¶ms->base, &prog_data->base.base, false, MESA_SHADER_TESS_CTRL); diff --git a/src/intel/compiler/brw_vec4_tcs.h b/src/intel/compiler/brw_vec4_tcs.h index 542b47e..e5de6c4 100644 --- a/src/intel/compiler/brw_vec4_tcs.h +++ b/src/intel/compiler/brw_vec4_tcs.h @@ -31,6 +31,7 @@ #define BRW_VEC4_TCS_H #include "brw_compiler.h" +#include "brw_eu.h" #include "brw_vec4.h" #ifdef __cplusplus -- 2.7.4