From a55070dbddf4773cfb4be85ae0d5dcc84a195e73 Mon Sep 17 00:00:00 2001
From: Colin LeMahieu <colinl@codeaurora.org>
Date: Mon, 8 Dec 2014 17:01:18 +0000
Subject: [PATCH] [Hexagon] Adding packhl instruction.

llvm-svn: 223664
---
 llvm/lib/Target/Hexagon/HexagonInstrInfo.td      | 6 ++++++
 llvm/test/MC/Disassembler/Hexagon/alu32_perm.txt | 2 ++
 2 files changed, 8 insertions(+)

diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td
index 14dfad1..3158adc 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td
@@ -204,6 +204,12 @@ def: BinOp32_pat<or,  A2_or,  i32>;
 def: BinOp32_pat<sub, A2_sub, i32>;
 def: BinOp32_pat<xor, A2_xor, i32>;
 
+// A few special cases producing register pairs:
+let OutOperandList = (outs DoubleRegs:$Rd), hasNewValue = 0,
+    isCodeGenOnly = 0 in {
+  def S2_packhl    : T_ALU32_3op  <"packhl",  0b101, 0b100, 0, 0>;
+}
+
 let hasSideEffects = 0, hasNewValue = 1, isCompare = 1, InputType = "reg"  in
 class T_ALU32_3op_cmp<string mnemonic, bits<2> MinOp, bit IsNeg, bit IsComm>
   : ALU32_rr<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
diff --git a/llvm/test/MC/Disassembler/Hexagon/alu32_perm.txt b/llvm/test/MC/Disassembler/Hexagon/alu32_perm.txt
index fce6f8d..2f1d1b6 100644
--- a/llvm/test/MC/Disassembler/Hexagon/alu32_perm.txt
+++ b/llvm/test/MC/Disassembler/Hexagon/alu32_perm.txt
@@ -22,3 +22,5 @@
 # CHECK: r17 = aslh(r21)
 0x11 0xc0 0x35 0x70
 # CHECK: r17 = asrh(r21)
+0x10 0xdf 0x95 0xf5
+# CHECK: r17:16 = packhl(r21, r31)
-- 
2.7.4