From a53f89545d62a27443f2d836be81ec6db68d12fd Mon Sep 17 00:00:00 2001 From: Jian Hu Date: Thu, 14 Jun 2018 17:44:24 +0800 Subject: [PATCH] clk: txl: initial add clock driver PD#168480: clk: txl: initial add clock driver remove CLK_SET_RATE_PARENT flag for spicc. If add CLK_SET_RATE_PARENT, it will change clk81 rate when set spicc clock rate. Change-Id: I80fec2c6d10611994ff40b06307e39b51ddb5a1a Signed-off-by: Jian Hu Signed-off-by: Bo Yang --- .../bindings/clock/amlogic,meson-clkc.txt | 4 +- MAINTAINERS | 6 + drivers/amlogic/clk/Makefile | 1 + drivers/amlogic/clk/clk_measure.c | 114 +++ drivers/amlogic/clk/clkc.h | 5 + drivers/amlogic/clk/txl/Makefile | 8 + drivers/amlogic/clk/txl/txl.c | 1025 ++++++++++++++++++++ drivers/amlogic/clk/txl/txl.h | 307 ++++++ drivers/amlogic/clk/txl/txl_ao.c | 141 +++ drivers/amlogic/clk/txl/txl_clk_gpu.c | 105 ++ drivers/amlogic/clk/txl/txl_clk_media.c | 750 ++++++++++++++ drivers/amlogic/clk/txl/txl_clk_sdemmc.c | 90 ++ include/dt-bindings/clock/amlogic,txl-clkc.h | 269 +++++ 13 files changed, 2824 insertions(+), 1 deletion(-) create mode 100644 drivers/amlogic/clk/txl/Makefile create mode 100644 drivers/amlogic/clk/txl/txl.c create mode 100644 drivers/amlogic/clk/txl/txl.h create mode 100644 drivers/amlogic/clk/txl/txl_ao.c create mode 100644 drivers/amlogic/clk/txl/txl_clk_gpu.c create mode 100644 drivers/amlogic/clk/txl/txl_clk_media.c create mode 100644 drivers/amlogic/clk/txl/txl_clk_sdemmc.c create mode 100644 include/dt-bindings/clock/amlogic,txl-clkc.h diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,meson-clkc.txt index a65f692..7f42f88 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,meson-clkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,meson-clkc.txt @@ -10,13 +10,15 @@ Required Properties: "amlogic,gxl-clkc" - for gxl ee clock "amlogic,axg-clkc" - for axg ee clock "amlogic,axg-aoclkc" - for axg ao clock + "amlogic,txl-clkc" - for txl ee clock + "amlogic,txl-aoclkc" - for txl ao clock "amlogic,txlx-clkc" - for txlx ee clock "amlogic,txlx-aoclkc" - for txlx ao clock "amlogic,g12a-clkc" - for g12a ee clock "amlogic,g12a-aoclkc" - for g12a ao clock "amlogic,g12b-clkc-1" - for g12b ee part1 clock "amlogic,g12b-clkc-2" - for g12b ee part2 clock - "amlogic,g12b-aoclkc" - for g12b ao clock + "amlogic,g12b-aoclkc" - for g12b ao clock - reg: physical base address of the clock controller and length of memory mapped region. diff --git a/MAINTAINERS b/MAINTAINERS index 6804e66..70a4d79 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14520,3 +14520,9 @@ F: arch/arm64/boot/dts/amlogic/firmware_normal.dtsi F: arch/arm64/boot/dts/amlogic/partition_mbox_normal_P_32.dtsi F: arch/arm64/boot/dts/amlogic/partition_mbox_normal_P_64.dtsi F: arch/arm64/boot/dts/amlogic/partition_mbox_p241_P.dtsi + +AMLOGIC TXL CLOCK +M: Jian Hu +F: include/dt-bindings/clock/amlogic,txl-clkc.h +F: drivers/amlogic/clk/txl/* + diff --git a/drivers/amlogic/clk/Makefile b/drivers/amlogic/clk/Makefile index 6af6c25..f7090d4 100644 --- a/drivers/amlogic/clk/Makefile +++ b/drivers/amlogic/clk/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_AMLOGIC_GX_CLK) += clk-cpu.o clk-mpll.o clk_test.o clk-cpu-fclk-com obj-$(CONFIG_AMLOGIC_GX_CLK) += gxl/ obj-$(CONFIG_AMLOGIC_GX_CLK) += axg/ obj-$(CONFIG_AMLOGIC_GX_CLK) += txlx/ +obj-$(CONFIG_AMLOGIC_GX_CLK) += txl/ obj-$(CONFIG_AMLOGIC_GX_CLK) += g12a/ obj-$(CONFIG_AMLOGIC_GX_CLK) += g12b/ diff --git a/drivers/amlogic/clk/clk_measure.c b/drivers/amlogic/clk/clk_measure.c index 807942c..b89827c 100644 --- a/drivers/amlogic/clk/clk_measure.c +++ b/drivers/amlogic/clk/clk_measure.c @@ -602,6 +602,117 @@ int axg_clk_measure(struct seq_file *s, void *what, unsigned int index) return 0; } +int txl_clk_measure(struct seq_file *s, void *what, unsigned int index) +{ + static const char * const clk_table[] = { + [88] = "hdmirx_vid_clk", + [87] = "lvds_fifo_clk", + [86] = "hdmirx_phy_dtb[3]", + [85] = "hdmirx_phy_dtb[2]", + [84] = "hdmirx_phy_dtb[1]", + [83] = "hdmirx_phy_dtb[0]", + [82] = "Cts_ge2d_clk", + [81] = "Cts_vapbclk", + [80] = "Rng_ring_osc_clk[3]", + [79] = "Rng_ring_osc_clk[2]", + [78] = "Rng_ring_osc_clk[1]", + [77] = "Rng_ring_osc_clk[0]", + [76] = "cts_aoclk_int", + [75] = "cts_aoclkx2_int", + [74] = "cts_atv_dmd_vdac_clk", + [73] = "cts_pwm_C_clk", + [72] = "cts_pwm_D_clk", + [71] = "cts_pwm_E_clk", + [70] = "cts_pwm_F_clk", + [69] = "Cts_hdcp22_skp", + [68] = "Cts_hdcp22_esm", + [67] = "tvfe_sample_clk", + [66] = "cts_vid_lock_clk", + [65] = "atv_dmd_sys_clk", + [64] = "Cts_hdmirx_cfg_clk", + [63] = "adc_dpll_intclk", + [62] = "cts_hevc_clk", + [61] = "gpio_clk_msr", + [60] = "alt_32k_clk", + [59] = "cts_hcodec_clk", + [58] = "Hdmirx_aud_clk", + [57] = "Cts_hdmirx_audmeas", + [56] = "Cts_hdmirx_modet_clk", + [55] = "vid_pll_div_clk_out", + [54] = "Cts_hdmirx_arc_ref_clk", + [53] = "Sd_emmc_clk_A", + [52] = "Sd_emmc_clk_B", + [51] = "Sd_emmc_clk_C", + [50] = "Mp3_clk_out", + [49] = "mp2_clk_out", + [48] = "mp1_clk_out", + [47] = "ddr_dpll_pt_clk", + [46] = "cts_vpu_clk", + [45] = "cts_pwm_A_clk", + [44] = "cts_pwm_B_clk", + [43] = "fclk_div5", + [42] = "mp0_clk_out", + [41] = "eth_rx_clk_or_clk_rmii", + [40] = "cts_pcm_mclk", + [39] = "cts_pcm_sclk", + [38] = "Cts_vdin_meas_clk", + [37] = "cts_clk_i958", + [36] = "cts_hdmi_tx_pixel_clk", + [35] = "cts_mali_clk", + [34] = "adc_dpll_clk_b3", + [33] = "adc_dpll_clk_b2", + [32] = "cts_vdec_clk", + [31] = "MPLL_CLK_TEST_OUT", + [30] = "Hdmirx_audmeas_clk", + [29] = "Hdmirx_pix_clk", + [28] = "cts_sar_adc_clk", + [27] = "Hdmirx_mpll_div_clk", + [26] = "sc_clk_int", + [25] = "Hdmirx_tmds_clk", + [24] = "Hdmirx_aud_pll_clk", + [23] = "mmc_clk", + [22] = "eth_phy_ref_clk", + [21] = "i2s_clk_in_src0", + [20] = "rtc_osc_clk_out", + [19] = "adc_dpll_clka2", + [18] = "sys_cpu_clk_div16", + [17] = "sys_pll_div16", + [16] = "cts_FEC_CLK_2", + [15] = "cts_FEC_CLK_1", + [14] = "cts_FEC_CLK_0", + [13] = "cts_amclk", + [12] = "Cts_pdm_clk", + [11] = "mac_eth_tx_clk", + [10] = "cts_vdac_clk", + [9] = "cts_encl_clk", + [8] = "cts_encp_clk", + [7] = "clk81", + [6] = "cts_enci_clk", + [5] = "gp1_pll_clk", + [4] = "gp0_pll_clk", + [3] = "A53_ring_osc_clk", + [2] = "am_ring_osc_clk_out_ee[2]", + [1] = "am_ring_osc_clk_out_ee[1]", + [0] = "am_ring_osc_clk_out_ee[0]", + }; + int i; + int len = sizeof(clk_table)/sizeof(char *); + + if (index == 0xff) { + for (i = 0; i < len; i++) + seq_printf(s, "[%2d][%10d]%s\n", + i, gxbb_clk_util_clk_msr(i), + clk_table[i]); + return 0; + } + seq_printf(s, "[%10d]%s\n", gxbb_clk_util_clk_msr(index), + clk_table[index]); + clk_msr_index = 0xff; + + return 0; +} + + int txlx_clk_measure(struct seq_file *s, void *what, unsigned int index) { static const char * const clk_table[] = { @@ -1089,6 +1200,7 @@ int meson_clk_measure(unsigned int clk_mux) break; case MESON_CPU_MAJOR_ID_GXL: case MESON_CPU_MAJOR_ID_GXM: + case MESON_CPU_MAJOR_ID_TXL: case MESON_CPU_MAJOR_ID_TXLX: case MESON_CPU_MAJOR_ID_G12A: case MESON_CPU_MAJOR_ID_G12B: @@ -1119,6 +1231,8 @@ static int dump_clk(struct seq_file *s, void *what) gxm_clk_measure(s, what, clk_msr_index); else if (get_cpu_type() == MESON_CPU_MAJOR_ID_AXG) axg_clk_measure(s, what, clk_msr_index); + else if (get_cpu_type() == MESON_CPU_MAJOR_ID_TXL) + txl_clk_measure(s, what, clk_msr_index); else if (get_cpu_type() == MESON_CPU_MAJOR_ID_TXLX) txlx_clk_measure(s, what, clk_msr_index); else if (get_cpu_type() == MESON_CPU_MAJOR_ID_G12A) diff --git a/drivers/amlogic/clk/clkc.h b/drivers/amlogic/clk/clkc.h index 5a90fdb..300a2d0 100644 --- a/drivers/amlogic/clk/clkc.h +++ b/drivers/amlogic/clk/clkc.h @@ -281,6 +281,11 @@ void meson_txlx_sdemmc_init(void); void meson_txlx_media_init(void); void meson_init_gpu(void); +/*txl*/ +void meson_txl_sdemmc_init(void); +void meson_txl_media_init(void); +void meson_txl_gpu_init(void); + void meson_g12a_sdemmc_init(void); void meson_g12a_media_init(void); void meson_g12a_gpu_init(void); diff --git a/drivers/amlogic/clk/txl/Makefile b/drivers/amlogic/clk/txl/Makefile new file mode 100644 index 0000000..ff56d67 --- /dev/null +++ b/drivers/amlogic/clk/txl/Makefile @@ -0,0 +1,8 @@ +# +# Makefile for Meson AXG clk +# + +obj-$(CONFIG_AMLOGIC_GX_CLK) += txl.o txl_ao.o \ + txl_clk_sdemmc.o \ + txl_clk_media.o \ + txl_clk_gpu.o diff --git a/drivers/amlogic/clk/txl/txl.c b/drivers/amlogic/clk/txl/txl.c new file mode 100644 index 0000000..f743840 --- /dev/null +++ b/drivers/amlogic/clk/txl/txl.c @@ -0,0 +1,1025 @@ +/* + * drivers/amlogic/clk/txl/txl.c + * + * Copyright (C) 2018 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "../clkc.h" +#include "txl.h" + +static struct clk_onecell_data clk_data; + +static struct meson_clk_pll txl_fixed_pll = { + .m = { + .reg_off = HHI_MPLL_CNTL, + .shift = 0, + .width = 9, + }, + .n = { + .reg_off = HHI_MPLL_CNTL, + .shift = 9, + .width = 5, + }, + .od = { + .reg_off = HHI_MPLL_CNTL, + .shift = 16, + .width = 2, + }, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "fixed_pll", + .ops = &meson_clk_pll_ro_ops, + .parent_names = (const char *[]){ "xtal" }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct meson_clk_pll txl_sys_pll = { + .m = { + .reg_off = HHI_SYS_PLL_CNTL, + .shift = 0, + .width = 9, + }, + .n = { + .reg_off = HHI_SYS_PLL_CNTL, + .shift = 9, + .width = 5, + }, + .od = { + .reg_off = HHI_SYS_PLL_CNTL, + .shift = 16, + .width = 2, + }, + .rate_table = sys_pll_rate_table, + .rate_count = ARRAY_SIZE(sys_pll_rate_table), + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "sys_pll", + .ops = &meson_clk_pll_ops, + .parent_names = (const char *[]){ "xtal" }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct meson_clk_pll txl_gp0_pll = { + .m = { + .reg_off = HHI_GP0_PLL_CNTL, + .shift = 0, + .width = 9, + }, + .n = { + .reg_off = HHI_GP0_PLL_CNTL, + .shift = 9, + .width = 5, + }, + .od = { + .reg_off = HHI_GP0_PLL_CNTL, + .shift = 16, + .width = 2, + }, + .rate_table = txl_gp0_pll_rate_table, + .rate_count = ARRAY_SIZE(txl_gp0_pll_rate_table), + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "gp0_pll", + .ops = &meson_clk_pll_ops, + .parent_names = (const char *[]){ "xtal" }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct meson_clk_pll txl_gp1_pll = { + .m = { + .reg_off = HHI_GP1_PLL_CNTL, + .shift = 0, + .width = 9, + }, + .n = { + .reg_off = HHI_GP1_PLL_CNTL, + .shift = 9, + .width = 5, + }, + .od = { + .reg_off = HHI_GP1_PLL_CNTL, + .shift = 16, + .width = 2, + }, + .rate_table = txl_gp0_pll_rate_table, + /* concern later ,write gp1? */ + .rate_count = ARRAY_SIZE(txl_gp0_pll_rate_table), + /* concern later ,write gp1? */ + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "gp1_pll", + .ops = &meson_clk_pll_ops, + .parent_names = (const char *[]){ "xtal" }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +#if 0 +static struct meson_clk_pll txl_adc_pll = { + .m = { + .reg_off = HHI_ADC_PLL_CNTL, + .shift = 0, + .width = 9, + }, + .n = { + .reg_off = HHI_ADC_PLL_CNTL, + .shift = 9, + .width = 5, + }, + .od = { + .reg_off = HHI_ADC_PLL_CNTL, + .shift = 14, + .width = 2, + }, + .rate_table = sys_pll_rate_table, + .rate_count = ARRAY_SIZE(sys_pll_rate_table), + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "sys_pll", + .ops = &meson_clk_pll_ops, + .parent_names = (const char *[]){ "xtal" }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; +#endif + +/*txl fixed multiplier and divider clock*/ +static struct clk_fixed_factor txl_fclk_div2 = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div2", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "fixed_pll" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor txl_fclk_div3 = { + .mult = 1, + .div = 3, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div3", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "fixed_pll" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor txl_fclk_div4 = { + .mult = 1, + .div = 4, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div4", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "fixed_pll" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor txl_fclk_div5 = { + .mult = 1, + .div = 5, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div5", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "fixed_pll" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor txl_fclk_div7 = { + .mult = 1, + .div = 7, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div7", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "fixed_pll" }, + .num_parents = 1, + }, +}; + +static struct meson_clk_mpll txl_mpll0 = { + .sdm = { + .reg_off = HHI_MPLL_CNTL7, + .shift = 0, + .width = 14, + }, + .n2 = { + .reg_off = HHI_MPLL_CNTL7, + .shift = 16, + .width = 9, + }, + .sdm_en = 15, + .en_dds = 14, + .top_misc_reg = HHI_PLL_TOP_MISC, + .top_misc_bit = 0, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "mpll0", + .ops = &meson_clk_mpll_ops, + .parent_names = (const char *[]){ "fixed_pll" }, + .num_parents = 1, + }, +}; + +static struct meson_clk_mpll txl_mpll1 = { + .sdm = { + .reg_off = HHI_MPLL_CNTL8, + .shift = 0, + .width = 14, + }, + .n2 = { + .reg_off = HHI_MPLL_CNTL8, + .shift = 16, + .width = 9, + }, + .sdm_en = 15, + .en_dds = 14, + .top_misc_reg = HHI_PLL_TOP_MISC, + .top_misc_bit = 1, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "mpll1", + .ops = &meson_clk_mpll_ops, + .parent_names = (const char *[]){ "fixed_pll" }, + .num_parents = 1, + }, +}; + +static struct meson_clk_mpll txl_mpll2 = { + .sdm = { + .reg_off = HHI_MPLL_CNTL9, + .shift = 0, + .width = 14, + }, + .n2 = { + .reg_off = HHI_MPLL_CNTL9, + .shift = 16, + .width = 9, + }, + .sdm_en = 15, + .en_dds = 14, + .top_misc_reg = HHI_PLL_TOP_MISC, + .top_misc_bit = 2, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "mpll2", + .ops = &meson_clk_mpll_ops, + .parent_names = (const char *[]){ "fixed_pll" }, + .num_parents = 1, + }, +}; + +static struct meson_clk_mpll txl_mpll3 = { + .sdm = { + .reg_off = HHI_MPLL3_CNTL0, + .shift = 12, + .width = 14, + }, + .n2 = { + .reg_off = HHI_MPLL3_CNTL0, + .shift = 2, + .width = 9, + }, + .sdm_en = 11, + .en_dds = 0, + .top_misc_reg = HHI_PLL_TOP_MISC, + .top_misc_bit = 3, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "mpll3", + .ops = &meson_clk_mpll_ops, + .parent_names = (const char *[]){ "fixed_pll" }, + .num_parents = 1, + }, +}; + +static struct meson_clk_pll txl_hdmi_pll = { + .m = { + .reg_off = HHI_HDMI_PLL_CNTL, + .shift = 0, + .width = 9, + }, + .n = { + .reg_off = HHI_HDMI_PLL_CNTL, + .shift = 9, + .width = 5, + }, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "hdmi_pll", + .ops = &meson_clk_pll_ro_ops, + .parent_names = (const char *[]){ "xtal" }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +/* + * FIXME cpu clocks and the legacy composite clocks (e.g. clk81) are both PLL + * post-dividers and should be modelled with their respective PLLs via the + * forthcoming coordinated clock rates feature + */ +static u32 mux_table_cpu_p00[] = { 0, 1, 2 }; +static struct clk_mux txl_cpu_fixedpll_p00 = { + .reg = (void *)HHI_SYS_CPU_CLK_CNTL0, + .mask = 0x3, + .shift = 0, + .table = mux_table_cpu_p00, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "cpu_fixedpll_p00", + .ops = &meson_clk_cpu_ops, + .parent_names = (const char *[]){ "xtal", "fclk_div2", + "fclk_div3"}, + .num_parents = 3, + .flags = (CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED), + }, +}; + +static struct clk_divider txl_cpu_fixedpll_p01 = { + .reg = (void *)HHI_SYS_CPU_CLK_CNTL0, + .shift = 4, + .width = 6, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "cpu_fixedpll_p01", + .ops = &clk_divider_ops, + .parent_names = (const char *[]){ "cpu_fixedpll_p00" }, + .num_parents = 1, + .flags = (CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED), + }, +}; + +static u32 mux_table_cpu_p0[] = { 0, 1 }; +static struct clk_mux txl_cpu_fixedpll_p0 = { + .reg = (void *)HHI_SYS_CPU_CLK_CNTL0, + .mask = 0x1, + .shift = 2, + .table = mux_table_cpu_p0, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "cpu_fixedpll_p0", + .ops = &meson_clk_cpu_ops, + .parent_names = (const char *[]){ "cpu_fixedpll_p00", + "cpu_fixedpll_p01"}, + .num_parents = 2, + .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT + | CLK_IGNORE_UNUSED), + }, +}; + +static u32 mux_table_cpu_p10[] = { 0, 1, 2 }; +static struct clk_mux txl_cpu_fixedpll_p10 = { + .reg = (void *)HHI_SYS_CPU_CLK_CNTL0, + .mask = 0x3, + .shift = 16, + .table = mux_table_cpu_p10, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "cpu_fixedpll_p10", + .ops = &meson_clk_cpu_ops, + .parent_names = (const char *[]){ "xtal", "fclk_div2", + "fclk_div3"}, + .num_parents = 3, + .flags = (CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED), + }, +}; + +static struct clk_divider txl_cpu_fixedpll_p11 = { + .reg = (void *)HHI_SYS_CPU_CLK_CNTL0, + .shift = 20, + .width = 6, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "cpu_fixedpll_p11", + .ops = &clk_divider_ops, + .parent_names = (const char *[]){ "cpu_fixedpll_p10" }, + .num_parents = 1, + .flags = (CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED), + }, +}; + +static u32 mux_table_cpu_p1[] = { 0, 1 }; +static struct clk_mux txl_cpu_fixedpll_p1 = { + .reg = (void *)HHI_SYS_CPU_CLK_CNTL0, + .mask = 0x1, + .shift = 18, + .table = mux_table_cpu_p1, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "cpu_fixedpll_p1", + .ops = &meson_clk_cpu_ops, + .parent_names = (const char *[]){ "cpu_fixedpll_p10", + "cpu_fixedpll_p11"}, + .num_parents = 2, + .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT + | CLK_IGNORE_UNUSED), + }, +}; + +static u32 mux_table_cpu_p[] = { 0, 1 }; +static struct clk_mux txl_cpu_fixedpll_p = { + .reg = (void *)HHI_SYS_CPU_CLK_CNTL0, + .mask = 0x1, + .shift = 10, + .table = mux_table_cpu_p, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "cpu_fixedpll_p", + .ops = &meson_clk_cpu_ops, + .parent_names = (const char *[]){ "cpu_fixedpll_p0", + "cpu_fixedpll_p1"}, + .num_parents = 2, + .flags = (CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED), + }, +}; + +static u32 mux_table_cpu_clk[] = { 0, 1 }; +static struct meson_clk_cpu txl_cpu_clk = { + .reg_off = HHI_SYS_CPU_CLK_CNTL0, + .mux.reg = (void *)HHI_SYS_CPU_CLK_CNTL0, + .mux.shift = 11, + .mux.mask = 0x1, + .mux.lock = &clk_lock, + .mux.table = mux_table_cpu_clk, + .mux.hw.init = &(struct clk_init_data){ + .name = "cpu_clk", + .ops = &meson_clk_cpu_ops, + .parent_names = (const char *[]){ "cpu_fixedpll_p", "sys_pll"}, + .num_parents = 2, + .flags = (CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED), + }, +}; + +static u32 mux_table_clk81[] = { 6, 5, 7 }; + +static struct clk_mux txl_mpeg_clk_sel = { + .reg = (void *)HHI_MPEG_CLK_CNTL, + .mask = 0x7, + .shift = 12, + .flags = CLK_MUX_READ_ONLY, + .table = mux_table_clk81, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "mpeg_clk_sel", + .ops = &clk_mux_ro_ops, + /* + * FIXME bits 14:12 selects from 8 possible parents: + * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2, + * fclk_div4, fclk_div3, fclk_div5 + */ + .parent_names = (const char *[]){ "fclk_div3", "fclk_div4", + "fclk_div5" }, + .num_parents = 3, + .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED), + }, +}; + +static struct clk_divider txl_mpeg_clk_div = { + .reg = (void *)HHI_MPEG_CLK_CNTL, + .shift = 0, + .width = 7, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "mpeg_clk_div", + .ops = &clk_divider_ops, + .parent_names = (const char *[]){ "mpeg_clk_sel" }, + .num_parents = 1, + .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), + }, +}; + +/* the mother of dragons^W gates */ +static struct clk_gate txl_clk81 = { + .reg = (void *)HHI_MPEG_CLK_CNTL, + .bit_idx = 7, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "clk81", + .ops = &clk_gate_ops, + .parent_names = (const char *[]){ "mpeg_clk_div" }, + .num_parents = 1, + .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), + }, +}; + +static struct clk_gate txl_spicc_0 = { + .reg = (void *)HHI_GCLK_MPEG0, + .bit_idx = 8, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "txl_spicc_0", + .ops = &clk_gate_ops, + .parent_names = (const char *[]){ "clk81" }, + .num_parents = 1, + .flags = CLK_IGNORE_UNUSED, + }, +}; +/* Everything Else (EE) domain gates */ + +/*HHI_GCLK_MPEG0 bit 2,3,4,14,15,17,18,20,22,24,31 not use*/ +static MESON_GATE(txl_ddr, HHI_GCLK_MPEG0, 0); +static MESON_GATE(txl_dos, HHI_GCLK_MPEG0, 1); +static MESON_GATE(txl_isa, HHI_GCLK_MPEG0, 5); +static MESON_GATE(txl_pl301, HHI_GCLK_MPEG0, 6); +static MESON_GATE(txl_periphs, HHI_GCLK_MPEG0, 7); +//static MESON_GATE(txl_spicc_0, HHI_GCLK_MPEG0, 8); +static MESON_GATE(txl_i2c, HHI_GCLK_MPEG0, 9); +static MESON_GATE(txl_sana, HHI_GCLK_MPEG0, 10); +static MESON_GATE(txl_smart_card, HHI_GCLK_MPEG0, 11); +static MESON_GATE(txl_rng0, HHI_GCLK_MPEG0, 12); +static MESON_GATE(txl_uart0, HHI_GCLK_MPEG0, 13); +static MESON_GATE(txl_async_fifo, HHI_GCLK_MPEG0, 16); +static MESON_GATE(txl_hiu_reg, HHI_GCLK_MPEG0, 19); +static MESON_GATE(txl_hdmirx_apb, HHI_GCLK_MPEG0, 21); +static MESON_GATE(txl_assist_misc, HHI_GCLK_MPEG0, 23); +static MESON_GATE(txl_emmc_b, HHI_GCLK_MPEG0, 25); +static MESON_GATE(txl_emmc_c, HHI_GCLK_MPEG0, 26); +static MESON_GATE(txl_dma, HHI_GCLK_MPEG0, 27); +static MESON_GATE(txl_acodec, HHI_GCLK_MPEG0, 28); +static MESON_GATE(txl_atv_demod, HHI_GCLK_MPEG0, 29); +static MESON_GATE(txl_spi, HHI_GCLK_MPEG0, 30); + +/*HHI_GCLK_MPEG1 bit 1,5,14,17,18,19,24,27,28 not use*/ +static MESON_GATE(txl_pclk_tvfe, HHI_GCLK_MPEG1, 0); +static MESON_GATE(txl_i2s_spdif, HHI_GCLK_MPEG1, 2); +static MESON_GATE(txl_eth_core, HHI_GCLK_MPEG1, 3); +static MESON_GATE(txl_demux, HHI_GCLK_MPEG1, 4); +static MESON_GATE(txl_aiu_glue, HHI_GCLK_MPEG1, 6); +static MESON_GATE(txl_iec958, HHI_GCLK_MPEG1, 7); +static MESON_GATE(txl_i2s_out, HHI_GCLK_MPEG1, 8); +static MESON_GATE(txl_amclk_measure, HHI_GCLK_MPEG1, 9); +static MESON_GATE(txl_aififo2, HHI_GCLK_MPEG1, 10); +static MESON_GATE(txl_mixer, HHI_GCLK_MPEG1, 11); +static MESON_GATE(txl_mixer_iface, HHI_GCLK_MPEG1, 12); +static MESON_GATE(txl_adc, HHI_GCLK_MPEG1, 13); +static MESON_GATE(txl_aiu_top, HHI_GCLK_MPEG1, 15); +static MESON_GATE(txl_uart1, HHI_GCLK_MPEG1, 16); +static MESON_GATE(txl_g2d, HHI_GCLK_MPEG1, 20); +static MESON_GATE(txl_usb0, HHI_GCLK_MPEG1, 21); +static MESON_GATE(txl_usb1, HHI_GCLK_MPEG1, 22); +static MESON_GATE(txl_reset, HHI_GCLK_MPEG1, 23); +static MESON_GATE(txl_dos_parser, HHI_GCLK_MPEG1, 25); +static MESON_GATE(txl_usb_general, HHI_GCLK_MPEG1, 26); +static MESON_GATE(txl_ahb_arb0, HHI_GCLK_MPEG1, 29); +static MESON_GATE(txl_efuse, HHI_GCLK_MPEG1, 30); +static MESON_GATE(txl_boot_rom, HHI_GCLK_MPEG1, 31); + +/*HHI_GCLK_MPEG2 bit 0,3,4,5,6,7,9,14,16-2022-24,27,29,31 not use*/ +static MESON_GATE(txl_ahb_data_bus, HHI_GCLK_MPEG2, 1); +static MESON_GATE(txl_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); +static MESON_GATE(txl_usb1_to_ddr, HHI_GCLK_MPEG2, 8); +static MESON_GATE(txl_usb0_to_ddr, HHI_GCLK_MPEG2, 9); +static MESON_GATE(txl_aiu_pclk, HHI_GCLK_MPEG2, 10); +static MESON_GATE(txl_mmc_pclk, HHI_GCLK_MPEG2, 11); +static MESON_GATE(txl_hdmi_hdcp22, HHI_GCLK_MPEG2, 13); +static MESON_GATE(txl_uart2, HHI_GCLK_MPEG2, 15); +static MESON_GATE(txl_uart3, HHI_GCLK_MPEG2, 21); +static MESON_GATE(txl_vpu_intr, HHI_GCLK_MPEG2, 25); +static MESON_GATE(txl_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); +static MESON_GATE(txl_demod_tvfe, HHI_GCLK_MPEG2, 26); +static MESON_GATE(txl_gic, HHI_GCLK_MPEG2, 30); + +/*HHI_GCLK_OTHER bit 0,11,12,12,15,17,18,19,27,28,29,30,31 not use*/ +static MESON_GATE(txl_vclk2_venci0, HHI_GCLK_OTHER, 1); +static MESON_GATE(txl_vclk2_venci1, HHI_GCLK_OTHER, 2); +static MESON_GATE(txl_vclk2_vencp0, HHI_GCLK_OTHER, 3); +static MESON_GATE(txl_vclk2_vencp1, HHI_GCLK_OTHER, 4); +static MESON_GATE(txl_vclk2_venct0, HHI_GCLK_OTHER, 5); +static MESON_GATE(txl_vclk2_venct1, HHI_GCLK_OTHER, 6); +static MESON_GATE(txl_vclk2_other, HHI_GCLK_OTHER, 7); +static MESON_GATE(txl_vclk2_enci, HHI_GCLK_OTHER, 8); +static MESON_GATE(txl_vclk2_encp, HHI_GCLK_OTHER, 9); +static MESON_GATE(txl_dac_clk, HHI_GCLK_OTHER, 10); +static MESON_GATE(txl_aoclk_gate, HHI_GCLK_OTHER, 14); +static MESON_GATE(txl_iec958_gate, HHI_GCLK_OTHER, 16); +static MESON_GATE(txl_enc480p, HHI_GCLK_OTHER, 20); +static MESON_GATE(txl_rng1, HHI_GCLK_OTHER, 21); +static MESON_GATE(txl_vclk2_enct, HHI_GCLK_OTHER, 22); +static MESON_GATE(txl_vclk2_encl, HHI_GCLK_OTHER, 23); +static MESON_GATE(txl_vclk2_venclmmc, HHI_GCLK_OTHER, 24); +static MESON_GATE(txl_vclk2_vencl, HHI_GCLK_OTHER, 25); +static MESON_GATE(txl_vclk2_other1, HHI_GCLK_OTHER, 26); + +/* end Everything Else (EE) domain gates */ + +/* Always On (AO) domain gates */ + +static MESON_GATE(txl_ao_media_cpu, HHI_GCLK_AO, 0); +static MESON_GATE(txl_ao_ahb_sram, HHI_GCLK_AO, 1); +static MESON_GATE(txl_ao_ahb_bus, HHI_GCLK_AO, 2); +static MESON_GATE(txl_ao_iface, HHI_GCLK_AO, 3); +static MESON_GATE(txl_ao_i2c, HHI_GCLK_AO, 4); + +/* Array of all clocks provided by this provider */ + +static struct clk_hw *txl_clk_hws[] = { + [CLKID_SYS_PLL] = &txl_sys_pll.hw, + [CLKID_FIXED_PLL] = &txl_fixed_pll.hw, + [CLKID_GP0_PLL] = &txl_gp0_pll.hw, + [CLKID_GP1_PLL] = &txl_gp1_pll.hw, + /*[CLKID_ADC_PLL] = &txl_adc_pll.hw,*/ + [CLKID_FCLK_DIV2] = &txl_fclk_div2.hw, + [CLKID_FCLK_DIV3] = &txl_fclk_div3.hw, + [CLKID_FCLK_DIV4] = &txl_fclk_div4.hw, + [CLKID_FCLK_DIV5] = &txl_fclk_div5.hw, + [CLKID_FCLK_DIV7] = &txl_fclk_div7.hw, + [CLKID_MPEG_SEL] = &txl_mpeg_clk_sel.hw, + [CLKID_MPEG_DIV] = &txl_mpeg_clk_div.hw, + [CLKID_CLK81] = &txl_clk81.hw, + [CLKID_MPLL0] = &txl_mpll0.hw, + [CLKID_MPLL1] = &txl_mpll1.hw, + [CLKID_MPLL2] = &txl_mpll2.hw, + [CLKID_MPLL3] = &txl_mpll3.hw, + [CLKID_DDR] = &txl_ddr.hw, + /*HHI_GCLK_MPEG0 0*/ + [CLKID_DOS] = &txl_dos.hw, + /*HHI_GCLK_MPEG0 1*/ + [CLKID_ISA] = &txl_isa.hw, + /*HHI_GCLK_MPEG0 5*/ + [CLKID_PL301] = &txl_pl301.hw, + /*HHI_GCLK_MPEG0 6*/ + [CLKID_PERIPHS] = &txl_periphs.hw, + /*HHI_GCLK_MPEG0 7*/ + [CLKID_SPICC0] = &txl_spicc_0.hw, + /*HHI_GCLK_MPEG0 8*/ + [CLKID_I2C] = &txl_i2c.hw, + /*HHI_GCLK_MPEG0 9*/ + [CLKID_SANA] = &txl_sana.hw, + /*HHI_GCLK_MPEG0 10*/ + [CLKID_SMART_CARD] = &txl_smart_card.hw, + /*HHI_GCLK_MPEG0 11*/ + [CLKID_RNG0] = &txl_rng0.hw, + /*HHI_GCLK_MPEG0 12*/ + [CLKID_UART0] = &txl_uart0.hw, + /*HHI_GCLK_MPEG0 13*/ + [CLKID_ASYNC_FIFO] = &txl_async_fifo.hw, + /*HHI_GCLK_MPEG0 16*/ + [CLKID_HIU_REG] = &txl_hiu_reg.hw, + /*HHI_GCLK_MPEG0 19*/ + [CLKID_HDMIRX_APB] = &txl_hdmirx_apb.hw, + /*HHI_GCLK_MPEG0 21*/ + [CLKID_ASSIST_MISC] = &txl_assist_misc.hw, + /*HHI_GCLK_MPEG0 23*/ + [CLKID_SD_EMMC_B] = &txl_emmc_b.hw, + /*HHI_GCLK_MPEG0 25*/ + [CLKID_SD_EMMC_C] = &txl_emmc_c.hw, + /*HHI_GCLK_MPEG0 26*/ + [CLKID_DMA] = &txl_dma.hw, + /*HHI_GCLK_MPEG0 27*/ + [CLKID_ACODEC] = &txl_acodec.hw, + /*HHI_GCLK_MPEG0 28*/ + [CLKID_ATV_DEMOD] = &txl_atv_demod.hw, + /*HHI_GCLK_MPEG0 29*/ + [CLKID_SPI] = &txl_spi.hw, + /*HHI_GCLK_MPEG0 30*/ + + [CLKID_PCLK_TVFE] = &txl_pclk_tvfe.hw, + /*HHI_GCLK_MPEG1 0*/ + [CLKID_I2S_SPDIF] = &txl_i2s_spdif.hw, + /*HHI_GCLK_MPEG1 2*/ + [CLKID_ETH_CORE] = &txl_eth_core.hw, + /*HHI_GCLK_MPEG1 3*/ + [CLKID_DEMUX] = &txl_demux.hw, + /*HHI_GCLK_MPEG1 4*/ + [CLKID_AIU_GLUE] = &txl_aiu_glue.hw, + /*HHI_GCLK_MPEG1 6*/ + [CLKID_IEC958] = &txl_iec958.hw, + /*HHI_GCLK_MPEG1 7*/ + [CLKID_I2S_OUT] = &txl_i2s_out.hw, + /*HHI_GCLK_MPEG1 8*/ + [CLKID_AMCLK_MEASURE] = &txl_amclk_measure.hw, + /*HHI_GCLK_MPEG1 9*/ + [CLKID_AIFIFO2] = &txl_aififo2.hw, + /*HHI_GCLK_MPEG1 10*/ + [CLKID_MIXER] = &txl_mixer.hw, + /*HHI_GCLK_MPEG1 11*/ + [CLKID_MIXER_IFACE] = &txl_mixer_iface.hw, + /*HHI_GCLK_MPEG1 12*/ + [CLKID_ADC] = &txl_adc.hw, + /*HHI_GCLK_MPEG1 13*/ + [CLKID_AIU_TOP] = &txl_aiu_top.hw, + /*HHI_GCLK_MPEG1 15*/ + [CLKID_UART1] = &txl_uart1.hw, + /*HHI_GCLK_MPEG1 16*/ + [CLKID_G2D] = &txl_g2d.hw, + /*HHI_GCLK_MPEG1 20*/ + [CLKID_RESET] = &txl_reset.hw, + /*HHI_GCLK_MPEG1 21*/ + [CLKID_USB0] = &txl_usb0.hw, + /*HHI_GCLK_MPEG1 22*/ + [CLKID_USB1] = &txl_usb1.hw, + /*HHI_GCLK_MPEG1 23*/ + [CLKID_DOS_PARSER] = &txl_dos_parser.hw, + /*HHI_GCLK_MPEG1 25*/ + [CLKID_USB_GENERAL] = &txl_usb_general.hw, + /*HHI_GCLK_MPEG1 26*/ + [CLKID_AHB_ARB0] = &txl_ahb_arb0.hw, + /*HHI_GCLK_MPEG1 29*/ + [CLKID_EFUSE] = &txl_efuse.hw, + /*HHI_GCLK_MPEG1 30*/ + [CLKID_BOOT_ROM] = &txl_boot_rom.hw, + /*HHI_GCLK_MPEG1 31*/ + + [CLKID_AHB_DATA_BUS] = &txl_ahb_data_bus.hw, + /*HHI_GCLK_MPEG2 1*/ + [CLKID_AHB_CTRL_BUS] = &txl_ahb_ctrl_bus.hw, + /*HHI_GCLK_MPEG2 2*/ + [CLKID_USB1_TO_DDR] = &txl_usb1_to_ddr.hw, + /*HHI_GCLK_MPEG2 8*/ + [CLKID_USB0_TO_DDR] = &txl_usb0_to_ddr.hw, + /*HHI_GCLK_MPEG2 9*/ + [CLKID_AIU_PCLK] = &txl_aiu_pclk.hw, + /*HHI_GCLK_MPEG2 10*/ + [CLKID_MMC_PCLK] = &txl_mmc_pclk.hw, + /*HHI_GCLK_MPEG2 11*/ + [CLKID_HDMI_HDCP22] = &txl_hdmi_hdcp22.hw, + /*HHI_GCLK_MPEG2 13*/ + [CLKID_UART2] = &txl_uart2.hw, + /*HHI_GCLK_MPEG2 15*/ + [CLKID_UART3] = &txl_uart3.hw, + /*HHI_GCLK_MPEG2 21*/ + [CLKID_VPU_INTR] = &txl_vpu_intr.hw, + /*HHI_GCLK_MPEG2 25*/ + [CLKID_SEC_AHB_AHB3_BRIDGE] = &txl_sec_ahb_ahb3_bridge.hw, + /*HHI_GCLK_MPEG2 26*/ + [CLKID_DEMOD_TVFE] = &txl_demod_tvfe.hw, + /*HHI_GCLK_MPEG2 28*/ + [CLKID_GIC] = &txl_gic.hw, + /*HHI_GCLK_MPEG2 30*/ + + [CLKID_VCLK2_VENCI0] = &txl_vclk2_venci0.hw, + /*HHI_GCLK_OTHER 1*/ + [CLKID_VCLK2_VENCI1] = &txl_vclk2_venci1.hw, + /*HHI_GCLK_OTHER 2*/ + [CLKID_VCLK2_VENCP0] = &txl_vclk2_vencp0.hw, + /*HHI_GCLK_OTHER 3*/ + [CLKID_VCLK2_VENCP1] = &txl_vclk2_vencp1.hw, + /*HHI_GCLK_OTHER 4*/ + [CLKID_VCLK2_VENCT0] = &txl_vclk2_venct0.hw, + /*HHI_GCLK_OTHER 5*/ + [CLKID_VCLK2_VENCT1] = &txl_vclk2_venct1.hw, + /*HHI_GCLK_OTHER 6*/ + [CLKID_VCLK2_OTHER] = &txl_vclk2_other.hw, + /*HHI_GCLK_OTHER 7*/ + [CLKID_VCLK2_ENCI] = &txl_vclk2_enci.hw, + /*HHI_GCLK_OTHER 8*/ + [CLKID_VCLK2_ENCP] = &txl_vclk2_encp.hw, + /*HHI_GCLK_OTHER 9*/ + [CLKID_DAC_CLK] = &txl_dac_clk.hw, + /*HHI_GCLK_OTHER 10*/ + [CLKID_AOCLK_GATE] = &txl_aoclk_gate.hw, + /*HHI_GCLK_OTHER 14*/ + [CLKID_IEC958_GATE] = &txl_iec958_gate.hw, + /*HHI_GCLK_OTHER 16*/ + [CLKID_ENC480P] = &txl_enc480p.hw, + /*HHI_GCLK_OTHER 20*/ + [CLKID_RNG1] = &txl_rng1.hw, + /*HHI_GCLK_OTHER 21*/ + [CLKID_VCLK2_ENCT] = &txl_vclk2_enct.hw, + /*HHI_GCLK_OTHER 22*/ + [CLKID_VCLK2_ENCL] = &txl_vclk2_encl.hw, + /*HHI_GCLK_OTHER 23*/ + [CLKID_VCLK2_VENCLMMC] = &txl_vclk2_venclmmc.hw, + /*HHI_GCLK_OTHER 24*/ + [CLKID_VCLK2_VENCL] = &txl_vclk2_vencl.hw, + /*HHI_GCLK_OTHER 25*/ + [CLKID_VCLK2_OTHER1] = &txl_vclk2_other1.hw, + /*HHI_GCLK_OTHER 26*/ + + [CLKID_AO_MEDIA_CPU] = &txl_ao_media_cpu.hw, + [CLKID_AO_AHB_SRAM] = &txl_ao_ahb_sram.hw, + [CLKID_AO_AHB_BUS] = &txl_ao_ahb_bus.hw, + [CLKID_AO_IFACE] = &txl_ao_iface.hw, + [CLKID_AO_I2C] = &txl_ao_i2c.hw, + [CLKID_CPU_FCLK_P00] = &txl_cpu_fixedpll_p00.hw, + [CLKID_CPU_FCLK_P01] = &txl_cpu_fixedpll_p01.hw, + [CLKID_CPU_FCLK_P0] = &txl_cpu_fixedpll_p0.hw, + [CLKID_CPU_FCLK_P10] = &txl_cpu_fixedpll_p10.hw, + [CLKID_CPU_FCLK_P11] = &txl_cpu_fixedpll_p11.hw, + [CLKID_CPU_FCLK_P1] = &txl_cpu_fixedpll_p1.hw, + [CLKID_CPU_FCLK_P] = &txl_cpu_fixedpll_p.hw, + [CLKID_CPU_CLK] = &txl_cpu_clk.mux.hw, +}; +/* Convenience tables to populate base addresses in .probe */ + +static struct meson_clk_pll *const txl_clk_plls[] = { + &txl_fixed_pll, + &txl_sys_pll, + &txl_gp0_pll, + &txl_gp1_pll, + /*&txl_adc_pll,*/ + &txl_hdmi_pll, +}; + +static struct meson_clk_mpll *const txl_clk_mplls[] = { + &txl_mpll0, + &txl_mpll1, + &txl_mpll2, + &txl_mpll3, +}; + +static struct clk_gate *txl_clk_gates[] = { + &txl_clk81, + &txl_ddr, + &txl_dos, + &txl_isa, + &txl_pl301, + &txl_periphs, + &txl_spicc_0, + &txl_i2c, + &txl_sana, + &txl_smart_card, + &txl_rng0, + &txl_uart0, + &txl_async_fifo, + &txl_hiu_reg, + &txl_hdmirx_apb, + &txl_assist_misc, + &txl_emmc_b, + &txl_emmc_c, + &txl_dma, + &txl_acodec, + &txl_atv_demod, + &txl_spi, + &txl_pclk_tvfe, + &txl_i2s_spdif, + &txl_eth_core, + &txl_demux, + &txl_aiu_glue, + &txl_iec958, + &txl_i2s_out, + &txl_amclk_measure, + &txl_aififo2, + &txl_mixer, + &txl_mixer_iface, + &txl_adc, + &txl_aiu_top, + &txl_uart1, + &txl_usb0, + &txl_usb1, + &txl_g2d, + &txl_reset, + &txl_dos_parser, + &txl_usb_general, + &txl_ahb_arb0, + &txl_efuse, + &txl_boot_rom, + &txl_ahb_data_bus, + &txl_ahb_ctrl_bus, + &txl_usb1_to_ddr, + &txl_usb0_to_ddr, + &txl_aiu_pclk, + &txl_mmc_pclk, + &txl_hdmi_hdcp22, + &txl_uart2, + &txl_uart3, + &txl_vpu_intr, + &txl_sec_ahb_ahb3_bridge, + &txl_demod_tvfe, + &txl_gic, + &txl_vclk2_venci0, + &txl_vclk2_venci1, + &txl_vclk2_vencp0, + &txl_vclk2_vencp1, + &txl_vclk2_venct0, + &txl_vclk2_venct1, + &txl_vclk2_other, + &txl_vclk2_enci, + &txl_vclk2_encp, + &txl_dac_clk, + &txl_aoclk_gate, + &txl_iec958_gate, + &txl_enc480p, + &txl_rng1, + &txl_vclk2_enct, + &txl_vclk2_encl, + &txl_vclk2_venclmmc, + &txl_vclk2_vencl, + &txl_vclk2_other1, + &txl_ao_media_cpu, + &txl_ao_ahb_sram, + &txl_ao_ahb_bus, + &txl_ao_iface, + &txl_ao_i2c, +}; + +static void __init txl_clkc_init(struct device_node *np) +{ + int ret, clkid, i; + struct clk_hw *parent_hw; + struct clk *parent_clk; + + /* Generic clocks and PLLs */ + clk_base = of_iomap(np, 0); + if (!clk_base) { + pr_err("%s: Unable to map clk base\n", __func__); + return; + } + + /* Populate base address for PLLs */ + for (i = 0; i < ARRAY_SIZE(txl_clk_plls); i++) + txl_clk_plls[i]->base = clk_base; + + /* Populate base address for MPLLs */ + for (i = 0; i < ARRAY_SIZE(txl_clk_mplls); i++) + txl_clk_mplls[i]->base = clk_base; + + /* Populate the base address for CPU clk */ + txl_cpu_clk.mux.reg = clk_base + (u64)txl_cpu_clk.mux.reg; + txl_cpu_fixedpll_p00.reg = clk_base + (u64)txl_cpu_fixedpll_p00.reg; + txl_cpu_fixedpll_p01.reg = clk_base + (u64)txl_cpu_fixedpll_p01.reg; + txl_cpu_fixedpll_p10.reg = clk_base + (u64)txl_cpu_fixedpll_p10.reg; + txl_cpu_fixedpll_p11.reg = clk_base + (u64)txl_cpu_fixedpll_p11.reg; + txl_cpu_fixedpll_p0.reg = clk_base + (u64)txl_cpu_fixedpll_p0.reg; + txl_cpu_fixedpll_p1.reg = clk_base + (u64)txl_cpu_fixedpll_p1.reg; + txl_cpu_fixedpll_p.reg = clk_base + (u64)txl_cpu_fixedpll_p.reg; + + /* Populate the base address for the MPEG clks */ + txl_mpeg_clk_sel.reg = clk_base + (u64)txl_mpeg_clk_sel.reg; + txl_mpeg_clk_div.reg = clk_base + (u64)txl_mpeg_clk_div.reg; + + /* Populate base address for gates */ + for (i = 0; i < ARRAY_SIZE(txl_clk_gates); i++) + txl_clk_gates[i]->reg = clk_base + + (u64)txl_clk_gates[i]->reg; + + if (!clks) { + clks = kzalloc(NR_CLKS*sizeof(struct clk *), GFP_KERNEL); + if (!clks) { + pr_err("%s: alloc clks fail!", __func__); + return; + } + } else { + pr_err("%s: error: not kzalloc clks in eeclk!", __func__); + return; + } + + clk_data.clks = clks; + clk_data.clk_num = NR_CLKS; + + /*register all clks*/ + for (clkid = 0; clkid < CLOCK_GATE; clkid++) { + if (txl_clk_hws[clkid]) { + clks[clkid] = clk_register(NULL, txl_clk_hws[clkid]); + WARN_ON(IS_ERR(clks[clkid])); + } + } + + meson_txl_sdemmc_init(); + meson_txl_media_init(); + meson_init_gpu(); + + parent_hw = clk_hw_get_parent(&txl_cpu_clk.mux.hw); + parent_clk = parent_hw->clk; + ret = clk_notifier_register(parent_clk, &txl_cpu_clk.clk_nb); + if (ret) { + pr_err("%s: failed to register clock notifier for cpu_clk\n", + __func__); + goto iounmap; + } + + ret = of_clk_add_provider(np, of_clk_src_onecell_get, + &clk_data); + if (ret < 0) { + pr_err("%s fail ret: %d\n", __func__, ret); + return; + } + + return; + +iounmap: + iounmap(clk_base); + pr_err("%s iomap failed ret: %d\n", __func__, ret); +} + +CLK_OF_DECLARE(txl, "amlogic,txl-clkc", txl_clkc_init); diff --git a/drivers/amlogic/clk/txl/txl.h b/drivers/amlogic/clk/txl/txl.h new file mode 100644 index 0000000..6043652 --- /dev/null +++ b/drivers/amlogic/clk/txl/txl.h @@ -0,0 +1,307 @@ +/* + * drivers/amlogic/clk/txl/txl.h + * + * Copyright (C) 2018 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef __TXL_H +#define __TXL_H + +/* + * Clock controller register offsets + * + * Register offsets from the data sheet are listed in comment blocks below. + * Those offsets must be multiplied by 4 before adding them to the base address + * to get the right value + */ +/*ok*/ +#define HHI_GP0_PLL_CNTL 0x40 /* 0x10 offset in data sheet */ +/*new*/ +#define HHI_GP1_PLL_CNTL 0x60 /* 0x18 offset in data sheet */ +/*not define in spec*/ +#define HHI_HIFI_PLL_CNTL 0x80 /* 0x20 offset in data sheet */ + +#define HHI_PCIE_PLL_CNTL 0xd8 /* 0x36 offset in data sheet */ +#define HHI_PCIE_PLL_CNTL1 0xdc /* 0x37 offset in data sheet */ +#define HHI_PCIE_PLL_CNTL6 0xf0 /* 0x3c offset in data sheet */ + +#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */ +#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */ +#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */ +#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */ + +#define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */ + +#define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */ +#define HHI_SPICC_HCLK_CNTL 0x168 /* 0x5a offset in data sheet */ + +#define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */ +#define HHI_AUD_CLK_CNTL 0x178 /* 0x5e offset in data sheet */ +#define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */ +#define HHI_AUD_CLK_CNTL2 0x190 /* 0x64 offset in data sheet */ +#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */ +#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */ +#define HHI_AUD_CLK_CNTL3 0x1A4 /* 0x69 offset in data sheet */ +#define HHI_AUD_CLK_CNTL4 0x1A8 /* 0x6a offset in data sheet */ +#define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in data sheet */ +#define HHI_VPU_CLK_CNTL 0x1bC /* 0x6f offset in data sheet */ + +#define HHI_DEMOD_CLK_CNTL 0x1D0 /* 0x74 offset in data sheet */ +#define HHI_VDEC_CLK_CNTL 0x1E0 /* 0x78 offset in data sheet */ +#define HHI_VDEC2_CLK_CNTL 0x1E4 /* 0x79 offset in data sheet */ +#define HHI_VDEC3_CLK_CNTL 0x1E8 /* 0x7a offset in data sheet */ +#define HHI_VDEC4_CLK_CNTL 0x1EC /* 0x7b offset in data sheet */ +#define HHI_HDCP22_CLK_CNTL 0x1F0 /* 0x7c offset in data sheet */ +#define HHI_VAPBCLK_CNTL 0x1F4 /* 0x7d offset in data sheet */ +#define HHI_HDMIRX_CLK_CNTL 0x200 /* 0x80 offset in data sheet */ +#define HHI_HDMIRX_AUD_CLK_CNTL 0x204 /* 0x81 offset in data sheet */ +#define HHI_VPU_CLKB_CNTL 0x20C /* 0x83 offset in data sheet */ +#define HHI_32K_CLK_CNTL 0x224 /* 0x89 offset in data sheet */ +#define HHI_ALOCKER_CLK_CNTL 0x234 /* 0x8d offset in data sheet */ + +#define HHI_VDIN_MEAS_CLK_CNTL 0x250 /* 0x94 offset in data sheet */ +#define HHI_PCM_CLK_CNTL 0x258 /* 0x96 offset in data sheet */ +#define HHI_NAND_CLK_CNTL 0x25C /* 0x97 offset in data sheet */ +#define HHI_SD_EMMC_CLK_CNTL 0x264 /* 0x99 offset in data sheet */ + +#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ +#define HHI_MPLL_CNTL2 0x284 /* 0xa1 offset in data sheet */ +#define HHI_MPLL_CNTL3 0x288 /* 0xa2 offset in data sheet */ +#define HHI_MPLL_CNTL4 0x28C /* 0xa3 offset in data sheet */ +#define HHI_MPLL_CNTL5 0x290 /* 0xa4 offset in data sheet */ +#define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */ +#define HHI_MPLL_CNTL7 0x298 /* MP0, 0xa6 offset */ +#define HHI_MPLL_CNTL8 0x29C /* MP1, 0xa7 offset */ +#define HHI_MPLL_CNTL9 0x2A0 /* MP2, 0xa8 offset */ +#define HHI_MPLL_CNTL10 0x2A4 /* MP2, 0xa9 offset */ + +#define HHI_MPLL3_CNTL0 0x2E0 /* 0xb8 offset in data sheet */ +#define HHI_MPLL3_CNTL1 0x2E4 /* 0xb9 offset in data sheet */ +#define HHI_PLL_TOP_MISC 0x2E8 /* 0xba offset in data sheet */ + +#define HHI_ADC_PLL_CNTL 0x2A8 /* 0xaa offset in data sheet */ +#define HHI_ADC_PLL_CNTL2 0x2AC /* 0xab offset in data sheet */ +#define HHI_ADC_PLL_CNTL3 0x2B0 /* 0xac offset in data sheet */ +#define HHI_ADC_PLL_CNTL4 0x2B4 /* 0xad offset in data sheet */ + +#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */ +#define HHI_SYS_PLL_CNTL2 0x304 /* 0xc1 offset in data sheet */ +#define HHI_SYS_PLL_CNTL3 0x308 /* 0xc2 offset in data sheet */ +#define HHI_SYS_PLL_CNTL4 0x30c /* 0xc3 offset in data sheet */ +#define HHI_SYS_PLL_CNTL5 0x310 /* 0xc4 offset in data sheet */ + +#define HHI_HDMI_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ +#define HHI_HDMI_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */ +#define HHI_HDMI_PLL_CNTL3 0x328 /* 0xca offset in data sheet */ +#define HHI_HDMI_PLL_CNTL4 0x32C /* 0xcb offset in data sheet */ +#define HHI_HDMI_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */ + +#define HHI_VID_LOCK_CLK_CNTL 0x3c8 /* 0xf2 offset in data sheet */ +#define HHI_ATV_DMD_SYS_CLK_CNTL 0x3cc /* 0xf3 offset in data sheet */ +/* 0xf3 offset in data sheet */ +#define HHI_EE_MISC_CNTL 0x3d0 + +/* AO registers*/ +#define AO_RTI_PWR_CNTL_REG0 0x10 /* 0x4 offset in data sheet */ +#define AO_SAR_CLK 0x90 /* 0x24 offset in data sheet */ + +static const struct pll_rate_table sys_pll_rate_table[] = { + PLL_RATE(24000000, 56, 1, 2), + PLL_RATE(48000000, 64, 1, 2), + PLL_RATE(72000000, 72, 1, 2), + PLL_RATE(96000000, 64, 1, 2), + PLL_RATE(120000000, 80, 1, 2), + PLL_RATE(144000000, 96, 1, 2), + PLL_RATE(168000000, 56, 1, 1), + PLL_RATE(192000000, 64, 1, 1), + PLL_RATE(216000000, 72, 1, 1), + PLL_RATE(240000000, 80, 1, 1), + PLL_RATE(264000000, 88, 1, 1), + PLL_RATE(288000000, 96, 1, 1), + PLL_RATE(312000000, 52, 1, 2), + PLL_RATE(336000000, 56, 1, 2), + PLL_RATE(360000000, 60, 1, 2), + PLL_RATE(384000000, 64, 1, 2), + PLL_RATE(408000000, 68, 1, 2), + PLL_RATE(432000000, 72, 1, 2), + PLL_RATE(456000000, 76, 1, 2), + PLL_RATE(480000000, 80, 1, 2), + PLL_RATE(504000000, 84, 1, 2), + PLL_RATE(528000000, 88, 1, 2), + PLL_RATE(552000000, 92, 1, 2), + PLL_RATE(576000000, 96, 1, 2), + PLL_RATE(600000000, 50, 1, 1), + PLL_RATE(624000000, 52, 1, 1), + PLL_RATE(648000000, 54, 1, 1), + PLL_RATE(672000000, 56, 1, 1), + PLL_RATE(696000000, 58, 1, 1), + PLL_RATE(720000000, 60, 1, 1), + PLL_RATE(744000000, 62, 1, 1), + PLL_RATE(768000000, 64, 1, 1), + PLL_RATE(792000000, 66, 1, 1), + PLL_RATE(816000000, 68, 1, 1), + PLL_RATE(840000000, 70, 1, 1), + PLL_RATE(864000000, 72, 1, 1), + PLL_RATE(888000000, 74, 1, 1), + PLL_RATE(912000000, 76, 1, 1), + PLL_RATE(936000000, 78, 1, 1), + PLL_RATE(960000000, 80, 1, 1), + PLL_RATE(984000000, 82, 1, 1), + PLL_RATE(1008000000, 84, 1, 1), + PLL_RATE(1032000000, 86, 1, 1), + PLL_RATE(1056000000, 88, 1, 1), + PLL_RATE(1080000000, 90, 1, 1), + PLL_RATE(1104000000, 92, 1, 1), + PLL_RATE(1128000000, 94, 1, 1), + PLL_RATE(1152000000, 96, 1, 1), + PLL_RATE(1176000000, 98, 1, 1), + PLL_RATE(1200000000, 50, 1, 0), + PLL_RATE(1224000000, 51, 1, 0), + PLL_RATE(1248000000, 52, 1, 0), + PLL_RATE(1272000000, 53, 1, 0), + PLL_RATE(1296000000, 54, 1, 0), + PLL_RATE(1320000000, 55, 1, 0), + PLL_RATE(1344000000, 56, 1, 0), + PLL_RATE(1368000000, 57, 1, 0), + PLL_RATE(1392000000, 58, 1, 0), + PLL_RATE(1416000000, 59, 1, 0), + PLL_RATE(1440000000, 60, 1, 0), + PLL_RATE(1464000000, 61, 1, 0), + PLL_RATE(1488000000, 62, 1, 0), + PLL_RATE(1512000000, 63, 1, 0), + PLL_RATE(1536000000, 64, 1, 0), + PLL_RATE(1560000000, 65, 1, 0), + PLL_RATE(1584000000, 66, 1, 0), + PLL_RATE(1608000000, 67, 1, 0), + PLL_RATE(1632000000, 68, 1, 0), + PLL_RATE(1656000000, 68, 1, 0), + PLL_RATE(1680000000, 68, 1, 0), + PLL_RATE(1704000000, 68, 1, 0), + PLL_RATE(1728000000, 69, 1, 0), + PLL_RATE(1752000000, 69, 1, 0), + PLL_RATE(1776000000, 69, 1, 0), + PLL_RATE(1800000000, 69, 1, 0), + PLL_RATE(1824000000, 70, 1, 0), + PLL_RATE(1848000000, 70, 1, 0), + PLL_RATE(1872000000, 70, 1, 0), + PLL_RATE(1896000000, 70, 1, 0), + PLL_RATE(1920000000, 71, 1, 0), + PLL_RATE(1944000000, 71, 1, 0), + PLL_RATE(1968000000, 71, 1, 0), + PLL_RATE(1992000000, 71, 1, 0), + PLL_RATE(2016000000, 72, 1, 0), + PLL_RATE(2040000000, 72, 1, 0), + PLL_RATE(2064000000, 72, 1, 0), + PLL_RATE(2088000000, 72, 1, 0), + PLL_RATE(2112000000, 73, 1, 0), + { /* sentinel */ }, +}; + +/*txl: gp0_pll: Fdco: 0.96G~1.632G Fdco = 24*(M+frac)/N + *N: recommend is 1 + *gp0_clk_out = Fdco /Fod + *od=0 Fod=1 od=1 Fod=2 od=2 Fod=4 od=3 Fod=4 + */ +static const struct pll_rate_table txl_gp0_pll_rate_table[] = { + PLL_RATE(240000000, 40, 1, 2), + PLL_RATE(246000000, 41, 1, 2), + PLL_RATE(252000000, 42, 1, 2), + PLL_RATE(258000000, 43, 1, 2), + PLL_RATE(264000000, 44, 1, 2), + PLL_RATE(270000000, 45, 1, 2), + PLL_RATE(276000000, 46, 1, 2), + PLL_RATE(282000000, 47, 1, 2), + PLL_RATE(288000000, 48, 1, 2), + PLL_RATE(294000000, 49, 1, 2), + PLL_RATE(300000000, 50, 1, 2), + PLL_RATE(306000000, 51, 1, 2), + PLL_RATE(312000000, 52, 1, 2), + PLL_RATE(318000000, 53, 1, 2), + PLL_RATE(324000000, 54, 1, 2), + PLL_RATE(330000000, 55, 1, 2), + PLL_RATE(336000000, 56, 1, 2), + PLL_RATE(342000000, 57, 1, 2), + PLL_RATE(348000000, 58, 1, 2), + PLL_RATE(354000000, 59, 1, 2), + PLL_RATE(360000000, 60, 1, 2), + PLL_RATE(366000000, 61, 1, 2), + PLL_RATE(372000000, 62, 1, 2), + PLL_RATE(378000000, 63, 1, 2), + PLL_RATE(384000000, 64, 1, 2), + PLL_RATE(390000000, 65, 1, 3), + PLL_RATE(396000000, 66, 1, 3), + PLL_RATE(402000000, 67, 1, 3), + PLL_RATE(408000000, 68, 1, 3), + PLL_RATE(480000000, 40, 1, 1), + PLL_RATE(492000000, 41, 1, 1), + PLL_RATE(504000000, 42, 1, 1), + PLL_RATE(516000000, 43, 1, 1), + PLL_RATE(528000000, 44, 1, 1), + PLL_RATE(540000000, 45, 1, 1), + PLL_RATE(552000000, 46, 1, 1), + PLL_RATE(564000000, 47, 1, 1), + PLL_RATE(576000000, 48, 1, 1), + PLL_RATE(588000000, 49, 1, 1), + PLL_RATE(600000000, 50, 1, 1), + PLL_RATE(612000000, 51, 1, 1), + PLL_RATE(624000000, 52, 1, 1), + PLL_RATE(636000000, 53, 1, 1), + PLL_RATE(648000000, 54, 1, 1), + PLL_RATE(660000000, 55, 1, 1), + PLL_RATE(672000000, 56, 1, 1), + PLL_RATE(684000000, 57, 1, 1), + PLL_RATE(696000000, 58, 1, 1), + PLL_RATE(708000000, 59, 1, 1), + PLL_RATE(720000000, 60, 1, 1), + PLL_RATE(732000000, 61, 1, 1), + PLL_RATE(744000000, 62, 1, 1), + PLL_RATE(756000000, 63, 1, 1), + PLL_RATE(768000000, 64, 1, 1), + PLL_RATE(780000000, 65, 1, 1), + PLL_RATE(792000000, 66, 1, 1), + PLL_RATE(804000000, 67, 1, 1), + PLL_RATE(816000000, 68, 1, 1), + PLL_RATE(960000000, 40, 1, 0), + PLL_RATE(984000000, 41, 1, 0), + PLL_RATE(1008000000, 42, 1, 0), + PLL_RATE(1032000000, 43, 1, 0), + PLL_RATE(1056000000, 44, 1, 0), + PLL_RATE(1080000000, 45, 1, 0), + PLL_RATE(1104000000, 46, 1, 0), + PLL_RATE(1128000000, 47, 1, 0), + PLL_RATE(1152000000, 48, 1, 0), + PLL_RATE(1176000000, 49, 1, 0), + PLL_RATE(1200000000, 50, 1, 0), + PLL_RATE(1224000000, 51, 1, 0), + PLL_RATE(1248000000, 52, 1, 0), + PLL_RATE(1272000000, 53, 1, 0), + PLL_RATE(1296000000, 54, 1, 0), + PLL_RATE(1320000000, 55, 1, 0), + PLL_RATE(1344000000, 56, 1, 0), + PLL_RATE(1368000000, 57, 1, 0), + PLL_RATE(1392000000, 58, 1, 0), + PLL_RATE(1416000000, 59, 1, 0), + PLL_RATE(1440000000, 60, 1, 0), + PLL_RATE(1464000000, 61, 1, 0), + PLL_RATE(1488000000, 62, 1, 0), + PLL_RATE(1512000000, 63, 1, 0), + PLL_RATE(1536000000, 64, 1, 0), + PLL_RATE(1560000000, 65, 1, 0), + PLL_RATE(1584000000, 66, 1, 0), + PLL_RATE(1608000000, 67, 1, 0), + PLL_RATE(1632000000, 68, 1, 0), + { /* sentinel */ }, +}; + +#endif /* __txl_H */ diff --git a/drivers/amlogic/clk/txl/txl_ao.c b/drivers/amlogic/clk/txl/txl_ao.c new file mode 100644 index 0000000..6fd0425 --- /dev/null +++ b/drivers/amlogic/clk/txl/txl_ao.c @@ -0,0 +1,141 @@ +/* + * drivers/amlogic/clk/txl/txl_ao.c + * + * Copyright (C) 2018 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "../clkc.h" +#include "txl.h" + +static struct clk_mux aoclk81 = { + .reg = (void *)AO_RTI_PWR_CNTL_REG0, + .mask = 0x1, + .shift = 8, + .flags = CLK_MUX_READ_ONLY, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "aoclk81", + .ops = &clk_mux_ops, + .parent_names = (const char *[]){ "clk81", "ao_slow_clk" }, + .num_parents = 2, + .flags = (CLK_SET_RATE_NO_REPARENT), + }, +}; + +/* sar_adc_clk */ +static struct clk_mux txl_saradc_mux = { + .reg = (void *)AO_SAR_CLK, + .mask = 0x3, + .shift = 9, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "txl_saradc_mux", + .ops = &clk_mux_ops, + .parent_names = (const char *[]){ "xtal", "aoclk81"}, + .num_parents = 2, + .flags = (CLK_GET_RATE_NOCACHE), + }, +}; + +static struct clk_divider txl_saradc_div = { + .reg = (void *)AO_SAR_CLK, + .shift = 0, + .width = 8, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "txl_saradc_div", + .ops = &clk_divider_ops, + .parent_names = (const char *[]){ "txl_saradc_mux" }, + .num_parents = 1, + .flags = (CLK_DIVIDER_ROUND_CLOSEST), + }, +}; + +static struct clk_gate txl_saradc_gate = { + .reg = (void *)AO_SAR_CLK, + .bit_idx = 8, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "txl_saradc_gate", + .ops = &clk_gate_ops, + .parent_names = (const char *[]){ "txl_saradc_div" }, + .num_parents = 1, + .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), + }, +}; + +/* Array of all clocks provided by this provider */ + +static struct clk_hw *txl_ao_clk_hws[] = { + [CLKID_AO_CLK81 - CLKID_AO_CLK81] + = &aoclk81.hw, + [CLKID_SARADC_MUX - CLKID_AO_CLK81] + = &txl_saradc_mux.hw, + [CLKID_SARADC_DIV - CLKID_AO_CLK81] + = &txl_saradc_div.hw, + [CLKID_SARADC_GATE - CLKID_AO_CLK81] + = &txl_saradc_gate.hw, +}; + +static int txl_aoclkc_probe(struct platform_device *pdev) +{ + void __iomem *aoclk_base; + int clkid; + struct device *dev = &pdev->dev; + + /* Generic clocks and PLLs */ + aoclk_base = of_iomap(dev->of_node, 0); + if (!aoclk_base) { + pr_err("%s: Unable to map clk base\n", __func__); + return -ENXIO; + } + /* Populate the base address for ao clk */ + aoclk81.reg = aoclk_base + (u64)aoclk81.reg; + txl_saradc_mux.reg = aoclk_base + (u64)txl_saradc_mux.reg; + txl_saradc_div.reg = aoclk_base + (u64)txl_saradc_div.reg; + txl_saradc_gate.reg = aoclk_base + (u64)txl_saradc_gate.reg; + + for (clkid = CLKID_AO_BASE; clkid < NR_CLKS; clkid++) { + if (txl_ao_clk_hws[clkid-CLKID_AO_BASE]) { + clks[clkid] = clk_register(NULL, + txl_ao_clk_hws[clkid-CLKID_AO_BASE]); + WARN_ON(IS_ERR(clks[clkid])); + } + } + + return 0; +} + +static const struct of_device_id txl_aoclkc_match_table[] = { + { .compatible = "amlogic,txl-aoclkc" }, + { } +}; + +static struct platform_driver txl_aoclk_driver = { + .probe = txl_aoclkc_probe, + .driver = { + .name = "txl-aoclkc", + .of_match_table = txl_aoclkc_match_table, + }, +}; + +builtin_platform_driver(txl_aoclk_driver); diff --git a/drivers/amlogic/clk/txl/txl_clk_gpu.c b/drivers/amlogic/clk/txl/txl_clk_gpu.c new file mode 100644 index 0000000..b988a7c --- /dev/null +++ b/drivers/amlogic/clk/txl/txl_clk_gpu.c @@ -0,0 +1,105 @@ +/* + * drivers/amlogic/clk/txl/txl_clk_gpu.c + * + * Copyright (C) 2018 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "../clkc.h" +#include "txl.h" + +PNAME(gpus_parent_names) = { "xtal", "gp0_pll", "mpll2", "mpll1", + "fclk_div7", "fclk_div4", "fclk_div3", "fclk_div5"}; +PNAME(gpumux_parent_names) = { "gpu_p0_composite", "gpu_p1_composite"}; + +/* gpu p0 */ +static MUX(gpu_p0_mux, HHI_MALI_CLK_CNTL, 0x7, 9, gpus_parent_names, + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(gpu_p0_div, HHI_MALI_CLK_CNTL, 0, 7, "gpu_p0_mux", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(gpu_p0_gate, HHI_MALI_CLK_CNTL, 8, "gpu_p0_div", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +/* gpu p1 */ +static MUX(gpu_p1_mux, HHI_MALI_CLK_CNTL, 0x7, 25, gpus_parent_names, + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(gpu_p1_div, HHI_MALI_CLK_CNTL, 16, 7, "gpu_p1_mux", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(gpu_p1_gate, HHI_MALI_CLK_CNTL, 24, "gpu_p1_div", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); + +static MESON_MUX(gpu_mux, HHI_MALI_CLK_CNTL, 0x1, 31, +gpumux_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); + +/* for init mux/div/gate clocks reg base*/ +static struct clk_mux *txl_gpu_clk_muxes[] = { + &gpu_p0_mux, + &gpu_p1_mux, + &gpu_mux, +}; + +static struct clk_divider *txl_gpu_clk_divs[] = { + &gpu_p0_div, + &gpu_p1_div, +}; + +static struct clk_gate *txl_gpu_clk_gates[] = { + &gpu_p0_gate, + &gpu_p1_gate, +}; + +static struct meson_composite gpu_composite[] = { + {CLKID_GPU_P0_COMP, "gpu_p0_composite", + gpus_parent_names, ARRAY_SIZE(gpus_parent_names), + &gpu_p0_mux.hw, &gpu_p0_div.hw, + &gpu_p0_gate.hw, 0 + },/*gpu_p0*/ + + {CLKID_GPU_P1_COMP, "gpu_p1_composite", + gpus_parent_names, ARRAY_SIZE(gpus_parent_names), + &gpu_p1_mux.hw, &gpu_p1_div.hw, &gpu_p1_gate.hw, 0 + },/*gpu_p1*/ +}; +void meson_txl_gpu_init(void) +{ + int i, length; + + length = ARRAY_SIZE(gpu_composite); + /* Populate base address for gpu muxes, divs,gates */ + for (i = 0; i < ARRAY_SIZE(txl_gpu_clk_muxes); i++) + txl_gpu_clk_muxes[i]->reg = clk_base + + (u64)txl_gpu_clk_muxes[i]->reg; + for (i = 0; i < ARRAY_SIZE(txl_gpu_clk_divs); i++) + txl_gpu_clk_divs[i]->reg = clk_base + + (u64)txl_gpu_clk_divs[i]->reg; + for (i = 0; i < ARRAY_SIZE(txl_gpu_clk_gates); i++) + txl_gpu_clk_gates[i]->reg = clk_base + + (u64)txl_gpu_clk_gates[i]->reg; + + meson_clk_register_composite(clks, gpu_composite, length); + + clks[CLKID_GPU_MUX] = clk_register(NULL, &gpu_mux.hw); + WARN_ON(IS_ERR(clks[CLKID_GPU_MUX])); + + clk_set_parent(clks[CLKID_GPU_MUX], clks[CLKID_GPU_P0_COMP]); + clk_prepare_enable(clks[CLKID_GPU_P0_COMP]); + clk_prepare_enable(clks[CLKID_GPU_P1_COMP]); + clk_set_rate(clks[CLKID_GPU_MUX], 400000000); +} diff --git a/drivers/amlogic/clk/txl/txl_clk_media.c b/drivers/amlogic/clk/txl/txl_clk_media.c new file mode 100644 index 0000000..befd6930 --- /dev/null +++ b/drivers/amlogic/clk/txl/txl_clk_media.c @@ -0,0 +1,750 @@ +/* + * drivers/amlogic/clk/txl/txl_clk_media.c + * + * Copyright (C) 2018 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "../clkc.h" +#include "txl.h" + +/* cts_vdin_meas_clk */ +PNAME(meas_parent_names) = { "xtal", "fclk_div4", +"fclk_div3", "fclk_div5", "vid_pll", "vid2_pll", "null", "null" }; +static MUX(vdin_meas_mux, HHI_VDIN_MEAS_CLK_CNTL, 0x7, 9, meas_parent_names, + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(vdin_meas_div, HHI_VDIN_MEAS_CLK_CNTL, 0, 7, "vdin_meas_mux", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(vdin_meas_gate, HHI_VDIN_MEAS_CLK_CNTL, 20, "vdin_meas_div", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +/* cts_vpu_p0_clk */ +PNAME(vpu_parent_names) = { "fclk_div4", "fclk_div3", "fclk_div5", +"fclk_div7", "null", "null", "null", "gp1_pll"}; +static MUX(vpu_p0_mux, HHI_VPU_CLK_CNTL, 0x7, 9, vpu_parent_names, + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(vpu_p0_div, HHI_VPU_CLK_CNTL, 0, 7, "vpu_p0_mux", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(vpu_p0_gate, HHI_VPU_CLK_CNTL, 8, "vpu_p0_div", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +/* cts_vpu_p1_clk */ +static MUX(vpu_p1_mux, HHI_VPU_CLK_CNTL, 0x7, 25, vpu_parent_names, + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(vpu_p1_div, HHI_VPU_CLK_CNTL, 16, 7, "vpu_p1_mux", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(vpu_p1_gate, HHI_VPU_CLK_CNTL, 24, "vpu_p1_div", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +/* vpu_clkb_tmp */ +PNAME(vpu_clkb_parent_names) = { "vpu_mux", + "fclk_div5", "vid_pll", "fclk_div4" }; +static MUX(vpu_clkb_tmp_mux, HHI_VPU_CLKB_CNTL, 0x3, 20, +vpu_clkb_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(vpu_clkb_tmp_div, HHI_VPU_CLKB_CNTL, 16, 4, "vpu_clkb_tmp_mux", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(vpu_clkb_tmp_gate, HHI_VPU_CLKB_CNTL, 24, "vpu_clkb_tmp_div", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +/* vpu_clkb */ +PNAME(vpu_clkb_nomux_parent_names) = { "vpu_clkb_tmp_composite" }; +static DIV(vpu_clkb_div, HHI_VPU_CLKB_CNTL, 0, 8, "vpu_clkb_tmp_composite", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(vpu_clkb_gate, HHI_VPU_CLKB_CNTL, 8, "vpu_clkb_div", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +/* vpu mux clk */ +PNAME(vpu_mux_parent_names) = { "vpu_p0_composite", "vpu_p1_composite" }; +static MESON_MUX(vpu_mux, HHI_VPU_CLK_CNTL, 0x1, 31, + vpu_mux_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); + +/* cts_vapb p0 clk */ +static MUX(vapb_p0_mux, HHI_VAPBCLK_CNTL, 0x7, 9, vpu_parent_names, + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(vapb_p0_div, HHI_VAPBCLK_CNTL, 0, 7, "vapb_p0_mux", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(vapb_p0_gate, HHI_VAPBCLK_CNTL, 8, "vapb_p0_div", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +/* cts_vapb p1 clk */ +static MUX(vapb_p1_mux, HHI_VAPBCLK_CNTL, 0x7, 25, vpu_parent_names, + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(vapb_p1_div, HHI_VAPBCLK_CNTL, 16, 7, "vapb_p1_mux", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(vapb_p1_gate, HHI_VAPBCLK_CNTL, 24, "vapb_p1_div", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); + +/* cts_vapb mux clk */ +PNAME(vapb_mux_parent_names) = { "vapb_p0_composite", "vapb_p1_composite" }; +static MESON_MUX(vapb_mux, HHI_VAPBCLK_CNTL, 0x1, 31, +vapb_mux_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(ge2d_gate, HHI_VAPBCLK_CNTL, 30, "vapb_mux", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); + +/*cts vid lock clock*/ +PNAME(cts_vid_lock_parent_names) = { "xtal", "fclk_div4", +"fclk_div3", "fclk_div5" }; +static MUX(cts_vid_lock_mux, HHI_VID_LOCK_CLK_CNTL, 0x3, 8, +cts_vid_lock_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(cts_vid_lock_div, HHI_VID_LOCK_CLK_CNTL, 0, 7, "cts_vid_lock_mux", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(cts_vid_lock_gate, HHI_VID_LOCK_CLK_CNTL, 7, "cts_vid_lock_div", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); + +/*hdmirx cfg clock*/ +PNAME(hdmirx_parent_names) = { "xtal", "fclk_div4", "fclk_div3", "fclk_div5" }; +static MUX(hdmirx_cfg_mux, HHI_HDMIRX_CLK_CNTL, 0x3, 9, hdmirx_parent_names, + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(hdmirx_cfg_div, HHI_HDMIRX_CLK_CNTL, 0, 7, "hdmirx_cfg_mux", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(hdmirx_cfg_gate, HHI_HDMIRX_CLK_CNTL, 8, "hdmirx_cfg_div", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +/*hdmirx modet clock*/ +static MUX(hdmirx_modet_mux, HHI_HDMIRX_CLK_CNTL, +0x3, 25, hdmirx_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(hdmirx_modet_div, HHI_HDMIRX_CLK_CNTL, 16, 7, "hdmirx_modet_mux", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(hdmirx_modet_gate, HHI_HDMIRX_CLK_CNTL, 24, "hdmirx_modet_div", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); + +/*hdmirx audmeas clock*/ +PNAME(hdmirx_ref_parent_names) = { "fclk_div4", +"fclk_div3", "fclk_div5", "fclk_div7" }; +static MUX(hdmirx_audmeas_mux, HHI_HDMIRX_AUD_CLK_CNTL, 0x3, 9, +hdmirx_ref_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(hdmirx_audmeas_div, HHI_HDMIRX_AUD_CLK_CNTL, 0, 7, +"hdmirx_audmeas_mux", CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(hdmirx_audmeas_gate, HHI_HDMIRX_AUD_CLK_CNTL, 8, +"hdmirx_audmeas_div", CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +/* hdmirx acr clock*/ +static MUX(hdmirx_acr_mux, HHI_HDMIRX_AUD_CLK_CNTL, 0x3, 25, +hdmirx_ref_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(hdmirx_acr_div, HHI_HDMIRX_AUD_CLK_CNTL, 16, 7, "hdmirx_acr_mux", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(hdmirx_acr_gate, HHI_HDMIRX_AUD_CLK_CNTL, 24, "hdmirx_acr_div", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +/* hdcp22 skpclk*/ +PNAME(hdcp22_skp_parent_names) = { "xtal", +"fclk_div4", "fclk_div3", "fclk_div5" }; +static MUX(hdcp22_skp_mux, HHI_HDCP22_CLK_CNTL, +0x3, 25, hdcp22_skp_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(hdcp22_skp_div, HHI_HDCP22_CLK_CNTL, 16, 7, "hdcp22_skp_mux", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(hdcp22_skp_gate, HHI_HDCP22_CLK_CNTL, 24, "hdcp22_skp_div", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +/* hdcp22 esm clock */ +PNAME(hdcp22_esm_parent_names) = { "fclk_div7", +"fclk_div4", "fclk_div3", "fclk_div5" }; +static MUX(hdcp22_esm_mux, HHI_HDCP22_CLK_CNTL, 0x3, 9, +hdcp22_esm_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(hdcp22_esm_div, HHI_HDCP22_CLK_CNTL, 0, 7, "hdcp22_esm_mux", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(hdcp22_esm_gate, HHI_HDCP22_CLK_CNTL, 8, "hdcp22_esm_div", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); + +/* cts demod core clock */ +PNAME(cts_demod_parent_names) = { "xtal", +"fclk_div4", "fclk_div3", "adc_dpll_int"}; +static MUX(cts_demod_mux, HHI_DEMOD_CLK_CNTL, 0x3, 9, +cts_demod_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(cts_demod_div, HHI_DEMOD_CLK_CNTL, 0, 7, "cts_demod_mux", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(cts_demod_gate, HHI_DEMOD_CLK_CNTL, 8, "cts_demod_div", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); + +/* adc extclk in clock */ +PNAME(adc_extclk_in_parent_names) = { "xtal", "fclk_div4", "fclk_div3", +"fclk_div5", "fclk_div7", "mpll2", "gp0_pll", "gp1_pll" }; +static MUX(adc_extclk_in_mux, HHI_DEMOD_CLK_CNTL, 0x7, 25, +adc_extclk_in_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(adc_extclk_in_div, HHI_DEMOD_CLK_CNTL, 16, 7, "adc_extclk_in_mux", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(adc_extclk_in_gate, HHI_DEMOD_CLK_CNTL, 24, "adc_extclk_in_div", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); + +/* cts atv dmd clock */ +PNAME(cts_atv_dmd_parent_names) = { "null", "null", "adc_extclk_composite", +"null" }; +static MUX(cts_atv_dmd_mux, HHI_ATV_DMD_SYS_CLK_CNTL, 0x3, 8, +cts_atv_dmd_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(cts_atv_dmd_div, HHI_ATV_DMD_SYS_CLK_CNTL, 0, 7, "cts_atv_dmd_mux", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(cts_atv_dmd_gate, HHI_ATV_DMD_SYS_CLK_CNTL, 7, "cts_atv_dmd_div", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); + +/*vdec clock*/ +/* cts_vdec_clk */ +PNAME(dec_parent_names) = { "fclk_div4", "fclk_div3", +"fclk_div5", "fclk_div7", "mpll1", "mpll2", "gp0_pll", "xtal" }; +static MUX(vdec_p0_mux, HHI_VDEC_CLK_CNTL, 0x7, 9, dec_parent_names, + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(vdec_p0_div, HHI_VDEC_CLK_CNTL, 0, 7, "vdec_p0_mux", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(vdec_p0_gate, HHI_VDEC_CLK_CNTL, 8, "vdec_p0_div", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static MUX(vdec_p1_mux, HHI_VDEC3_CLK_CNTL, 0x7, 9, dec_parent_names, + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(vdec_p1_div, HHI_VDEC3_CLK_CNTL, 0, 7, "vdec_p1_mux", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(vdec_p1_gate, HHI_VDEC3_CLK_CNTL, 8, "vdec_p1_div", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); + +/* vdec_mux clk */ +PNAME(vdec_mux_parent_names) = { "vdec_p0_composite", "vdec_p1_composite" }; +static MESON_MUX(vdec_mux, HHI_VDEC3_CLK_CNTL, 0x1, 15, +vdec_mux_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); + +/* hcodev clock*/ +static MUX(hcodec_p0_mux, HHI_VDEC_CLK_CNTL, 0x7, 25, dec_parent_names, + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(hcodec_p0_div, HHI_VDEC_CLK_CNTL, 16, 7, "hcodec_p0_mux", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(hcodec_p0_gate, HHI_VDEC_CLK_CNTL, 24, "hcodec_p0_div", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static MUX(hcodec_p1_mux, HHI_VDEC3_CLK_CNTL, 0x7, 25, dec_parent_names, + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(hcodec_p1_div, HHI_VDEC3_CLK_CNTL, 16, 7, "hcodec_p1_mux", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(hcodec_p1_gate, HHI_VDEC3_CLK_CNTL, 24, "hcodec_p1_div", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); + +/* hcodec_mux clk */ +PNAME(hcodec_mux_parent_names) = { +"hcodec_p0_composite", "hcodec_p1_composite" }; +static MESON_MUX(hcodec_mux, HHI_VDEC3_CLK_CNTL, 0x1, 31, +hcodec_mux_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); + + +/* hevc clock */ +static MUX(hevc_p0_mux, HHI_VDEC2_CLK_CNTL, 0x7, 25, dec_parent_names, + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(hevc_p0_div, HHI_VDEC2_CLK_CNTL, 16, 7, "hevc_p0_mux", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(hevc_p0_gate, HHI_VDEC2_CLK_CNTL, 24, "hevc_p0_div", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static MUX(hevc_p1_mux, HHI_VDEC4_CLK_CNTL, 0x7, 25, dec_parent_names, + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(hevc_p1_div, HHI_VDEC4_CLK_CNTL, 16, 7, "hevc_p1_mux", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(hevc_p1_gate, HHI_VDEC4_CLK_CNTL, 24, "hevc_p1_div", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); + +/* hevc_mux clk */ +PNAME(hevc_mux_parent_names) = { "hevc_p0_composite", "hevc_p1_composite" }; +static MESON_MUX(hevc_mux, HHI_VDEC4_CLK_CNTL, 0x1, 31, +hevc_mux_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); + +/* audio clocks */ +/* cts amclk */ +PNAME(cts_amclk_parent_names) = { "hdmirx_aud_pll_clk", +"mpll0", "mpll1", "mpll2", "mpll3", "gp0_pll", "gp0_pll", "null" }; +static MUX(cts_amclk_mux, HHI_AUD_CLK_CNTL, 0x7, 9, cts_amclk_parent_names, + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(cts_amclk_div, HHI_AUD_CLK_CNTL, 0, 7, "cts_amclk_mux", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(cts_amclk_gate, HHI_AUD_CLK_CNTL, 8, "cts_amclk_div", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); + +/* cts_iec958_spdif clock + * |\ + * 0 | \ + * | |------- + * 1 | / + * |/ + * offset 0x64 + * when bit[27] = 0, cts_amclk_composite + * when bit[27] = 1, iec958_int_composite + */ +PNAME(cts_iec958_spdif_parent_names) = { +"cts_amclk_composite", "iec958_int_composite" }; +static MUX(cts_iec958_spdif, HHI_AUD_CLK_CNTL2, 0x1, 27, +cts_iec958_spdif_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); + +/* iec958_int_composite, bit27 = 1 + *PNAME(cts_iec958_int_parent_names) = { "hdmirx_aud_pll_clk", "mpll0", + *"mpll1", "mpll2", "mpll3", "gp0_pll", "gp1_pll", "null"}; + */ +PNAME(cts_iec958_int_parent_names) = { "hdmirx_aud_pll_clk", "mpll0", +"mpll1", "mpll2" }; +static MUX(cts_iec958_int_mux, HHI_AUD_CLK_CNTL2, 0x3, 25, +cts_iec958_int_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(cts_iec958_int_div, HHI_AUD_CLK_CNTL2, +16, 8, "cts_iec958_int_mux", CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(cts_iec958_int_gate, HHI_AUD_CLK_CNTL2, +24, "cts_iec958_int_div", CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); + +/* cts pdm*/ +PNAME(cts_pdm_parent_names) = { "cts_amclk_composite", "mpll0", +"mpll1", "mpll2", "mpll3", "gp0_pll", "gp1_pll", "hdmirx_aud_pll_clk"}; +static MUX(cts_pdm_mux, HHI_AUD_CLK_CNTL3, 0x7, 17, cts_pdm_parent_names, + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(cts_pdm_div, HHI_AUD_CLK_CNTL3, 0, 16, "cts_pdm_mux", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(cts_pdm_gate, HHI_AUD_CLK_CNTL3, 16, "cts_pdm_div", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +/* cts audin mclk */ +PNAME(cts_audin_mclk_parent_names) = { "vid2_pll", "mpll0", "mpll1", +"mpll2", "gp0_pll", "gp1_pll", "hdmirx_aud_pll_clk", "vid_pll"}; +static MUX(cts_audin_mclk_mux, HHI_AUD_CLK_CNTL4, 0x7, 12, +cts_audin_mclk_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(cts_audin_mclk_div, HHI_AUD_CLK_CNTL4, +0, 10, "cts_audin_mclk_mux", CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(cts_audin_mclk_gate, HHI_AUD_CLK_CNTL4, +15, "cts_audin_mclk_div", CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +/* cts audin sclk */ +PNAME(cts_audin_sclk_parent_names) = { "cts_audin_mclk_composite" }; +static DIV(cts_audin_sclk_div, HHI_AUD_CLK_CNTL4, +16, 7, "cts_audin_mclk_composite", CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(cts_audin_sclk_gate, HHI_AUD_CLK_CNTL4, +23, "cts_audin_sclk_div", CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +/* cts audin lrclk */ +PNAME(cts_audin_lrclk_parent_names) = { "cts_audin_sclk_composite" }; +static DIV(cts_audin_lrclk_div, HHI_AUD_CLK_CNTL4, +24, 7, "cts_audin_sclk_composite", CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(cts_audin_lrclk_gate, HHI_AUD_CLK_CNTL4, +31, "cts_audin_lrclk_div", CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); + + +/* cts alocker in clk*/ +PNAME(cts_alocker_in_parent_names) = { "cts_hdmirx_aud_pll_clk", +"cts_audin_mclk_composite", "audin_pcm_clk_in", "audin_hdmirx_aud_clk", +"audin_i2s_sclk_in_0", "audin_i2s_sclk_in_1", "audin_i2s_sclk_in_2", +"audin_i2s_sclk_in_3"}; +static MUX(cts_alocker_in_mux, HHI_ALOCKER_CLK_CNTL, 0x7, 9, +cts_alocker_in_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(cts_alocker_in_div, HHI_ALOCKER_CLK_CNTL, +0, 8, "cts_alocker_in_mux", CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(cts_alocker_in_gate, HHI_ALOCKER_CLK_CNTL, +8, "cts_alocker_in_div", CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +/* cts alocker out clk*/ +PNAME(cts_alocker_out_parent_names) = { +"cts_amclk_composite", "cts_clk_i958", "cts_aoclk_int", +"cts_pdm_composite", "cts_pcm_mclk_composite", +"cts_audin_mclk_composite", "cts_encp_clk", "cts_enci_clk" }; +static MUX(cts_alocker_out_mux, HHI_ALOCKER_CLK_CNTL, 0x7, 25, +cts_alocker_out_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(cts_alocker_out_div, HHI_ALOCKER_CLK_CNTL, +16, 8, "cts_alocker_out_mux", CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(cts_alocker_out_gate, HHI_ALOCKER_CLK_CNTL, +24, "cts_alocker_out_div", CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +/* cts pcm mclk */ +PNAME(cts_pcm_mclk_parent_names) = { +"mpll0", "mpll1", "mpll2", "fclk_div5" }; +static MUX(cts_pcm_mclk_mux, HHI_PCM_CLK_CNTL, 0x3, 10, +cts_pcm_mclk_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(cts_pcm_mclk_div, HHI_PCM_CLK_CNTL, 0, 9, "cts_pcm_mclk_mux", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(cts_pcm_mclk_gate, HHI_PCM_CLK_CNTL, 9, "cts_pcm_mclk_div", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +/* cts pcm sclk */ +PNAME(cts_pcm_sclk_parent_names) = { "cts_pcm_mclk_composite" }; +static DIV(cts_pcm_sclk_div, HHI_PCM_CLK_CNTL, +16, 6, "cts_pcm_mclk_composite", CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(cts_pcm_sclk_gate, HHI_PCM_CLK_CNTL, 22, "cts_pcm_sclk_div", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); + +/* alt 32k clk */ +PNAME(alt_32k_parent_names) = { "xtal", "null", "fclk_div3", "fclk_div5" }; +static MUX(alt_32k_mux, HHI_32K_CLK_CNTL, 0x3, 16, +alt_32k_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(alt_32k_div, HHI_32K_CLK_CNTL, 0, 14, "alt_32k_mux", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(alt_32k_gate, HHI_32K_CLK_CNTL, 15, "alt_32k_div", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); + +#if 0 +static struct clk_hw *media_vhec_mux[] = { + [CLKID_VDEC_MUX - CLKID_VDEC_MUX] = &vdec_mux.hw, + [CLKID_HCODEC_MUX - CLKID_VDEC_MUX] = &hcodec_mux.hw, + [CLKID_HEVC_MUX - CLKID_VDEC_MUX] = &hevc_mux.hw, +}; +#endif + +/* for init mux clocks reg base*/ +static struct clk_mux *txl_media_clk_muxes[] = { + &vdin_meas_mux, + &vpu_p0_mux, + &vpu_p1_mux, + &vpu_mux, + &vapb_p0_mux, + &vapb_p1_mux, + &vapb_mux, + &vpu_clkb_tmp_mux, + &cts_vid_lock_mux, + &hdmirx_cfg_mux, + &hdmirx_modet_mux, + &hdmirx_audmeas_mux, + &hdmirx_acr_mux, + &hdcp22_skp_mux, + &hdcp22_esm_mux, + &cts_demod_mux, + &adc_extclk_in_mux, + &cts_atv_dmd_mux, + &vdec_p0_mux, + &vdec_p1_mux, + &vdec_mux, + &hcodec_p0_mux, + &hcodec_p1_mux, + &hcodec_mux, + &hevc_p0_mux, + &hevc_p1_mux, + &hevc_mux, + &cts_amclk_mux, + &cts_iec958_int_mux, + &cts_iec958_spdif, + &cts_pdm_mux, + &cts_audin_mclk_mux, + &cts_alocker_in_mux, + &cts_alocker_out_mux, + &cts_pcm_mclk_mux, + &alt_32k_mux, +}; + +/* for init div clocks reg base*/ +static struct clk_divider *txl_media_clk_divs[] = { + &vdin_meas_div, + &vpu_p0_div, + &vpu_p1_div, + &vapb_p0_div, + &vapb_p1_div, + &vpu_clkb_tmp_div, + &vpu_clkb_div, + &cts_vid_lock_div, + &hdmirx_cfg_div, + &hdmirx_modet_div, + &hdmirx_audmeas_div, + &hdmirx_acr_div, + &hdcp22_skp_div, + &hdcp22_esm_div, + &cts_demod_div, + &adc_extclk_in_div, + &cts_atv_dmd_div, + &vdec_p0_div, + &vdec_p1_div, + &hcodec_p0_div, + &hcodec_p1_div, + &hevc_p0_div, + &hevc_p1_div, + &cts_amclk_div, + &cts_iec958_int_div, + &cts_pdm_div, + &cts_audin_mclk_div, + &cts_audin_sclk_div, + &cts_audin_lrclk_div, + &cts_alocker_in_div, + &cts_alocker_out_div, + &cts_pcm_mclk_div, + &cts_pcm_sclk_div, + &alt_32k_div, +}; + +/* for init gate clocks reg base*/ +static struct clk_gate *txl_media_clk_gates[] = { + &vdin_meas_gate, + &vpu_p0_gate, + &vpu_p1_gate, + &vapb_p0_gate, + &vapb_p1_gate, + &ge2d_gate, + &vpu_clkb_tmp_gate, + &vpu_clkb_gate, + &cts_vid_lock_gate, + &hdmirx_cfg_gate, + &hdmirx_modet_gate, + &hdmirx_audmeas_gate, + &hdmirx_acr_gate, + &hdcp22_skp_gate, + &hdcp22_esm_gate, + &cts_demod_gate, + &adc_extclk_in_gate, + &cts_atv_dmd_gate, + &vdec_p0_gate, + &vdec_p1_gate, + &hcodec_p0_gate, + &hcodec_p1_gate, + &hevc_p0_gate, + &hevc_p1_gate, + &cts_amclk_gate, + &cts_iec958_int_gate, + &cts_pdm_gate, + &cts_audin_mclk_gate, + &cts_audin_sclk_gate, + &cts_audin_lrclk_gate, + &cts_alocker_in_gate, + &cts_alocker_out_gate, + &cts_pcm_mclk_gate, + &cts_pcm_sclk_gate, + &alt_32k_gate, +}; + +static struct meson_composite m_composite[] = { + {CLKID_VPU_CLKB_TMP_COMP, "vpu_clkb_tmp_composite", + vpu_clkb_parent_names, ARRAY_SIZE(vpu_clkb_parent_names), + &vpu_clkb_tmp_mux.hw, &vpu_clkb_tmp_div.hw, + &vpu_clkb_tmp_gate.hw, 0 + },/*vpu_clkb_tmp*/ + + {CLKID_VPU_CLKB_COMP, "vpu_clkb_composite", + vpu_clkb_nomux_parent_names, ARRAY_SIZE(vpu_clkb_nomux_parent_names), + NULL, &vpu_clkb_div.hw, &vpu_clkb_gate.hw, 0 + },/*vpu_clkb*/ + + {CLKID_VDIN_MEAS_COMP, "vdin_meas_composite", + meas_parent_names, ARRAY_SIZE(meas_parent_names), + &vdin_meas_mux.hw, &vdin_meas_div.hw, + &vdin_meas_gate.hw, 0 + },/*vdin_meas*/ + + {CLKID_VPU_P0_COMP, "vpu_p0_composite", + vpu_parent_names, ARRAY_SIZE(vpu_parent_names), + &vpu_p0_mux.hw, &vpu_p0_div.hw, + &vpu_p0_gate.hw, 0 + },/* cts_vpu_clk p0*/ + + {CLKID_VPU_P1_COMP, "vpu_p1_composite", + vpu_parent_names, ARRAY_SIZE(vpu_parent_names), + &vpu_p1_mux.hw, &vpu_p1_div.hw, + &vpu_p1_gate.hw, 0 + }, + + {CLKID_VAPB_P0_COMP, "vapb_p0_composite", + vpu_parent_names, ARRAY_SIZE(vpu_parent_names), + &vapb_p0_mux.hw, &vapb_p0_div.hw, + &vapb_p0_gate.hw, 0 + }, + + {CLKID_VAPB_P1_COMP, "vapb_p1_composite", + vpu_parent_names, ARRAY_SIZE(vpu_parent_names), + &vapb_p1_mux.hw, &vapb_p1_div.hw, + &vapb_p1_gate.hw, 0 + }, + + {CLKID_HDMIRX_CFG_COMP, "hdmirx_cfg_composite", + hdmirx_parent_names, ARRAY_SIZE(hdmirx_parent_names), + &hdmirx_cfg_mux.hw, &hdmirx_cfg_div.hw, + &hdmirx_cfg_gate.hw, 0 + }, + + {CLKID_HDMIRX_MODET_COMP, "hdmirx_modet_composite", + hdmirx_parent_names, ARRAY_SIZE(hdmirx_parent_names), + &hdmirx_modet_mux.hw, &hdmirx_modet_div.hw, + &hdmirx_modet_gate.hw, 0 + }, + + {CLKID_HDMIRX_AUDMEAS_COMP, "hdmirx_audmeas_composite", + hdmirx_ref_parent_names, ARRAY_SIZE(hdmirx_ref_parent_names), + &hdmirx_audmeas_mux.hw, &hdmirx_audmeas_div.hw, + &hdmirx_audmeas_gate.hw, 0 + }, + + {CLKID_HDMIRX_ACR_COMP, "hdmirx_acr_composite", + hdmirx_ref_parent_names, ARRAY_SIZE(hdmirx_ref_parent_names), + &hdmirx_acr_mux.hw, &hdmirx_acr_div.hw, + &hdmirx_acr_gate.hw, 0 + }, + + {CLKID_HDCP22_SKP_COMP, "hdcp22_skp_composite", + hdcp22_skp_parent_names, ARRAY_SIZE(hdcp22_skp_parent_names), + &hdcp22_skp_mux.hw, &hdcp22_skp_div.hw, + &hdcp22_skp_gate.hw, 0 + }, + + {CLKID_HDCP22_ESM_COMP, "hdcp22_esm_composite", + hdcp22_esm_parent_names, ARRAY_SIZE(hdcp22_esm_parent_names), + &hdcp22_esm_mux.hw, &hdcp22_esm_div.hw, + &hdcp22_esm_gate.hw, 0 + }, + + {CLKID_VDEC_P0_COMP, "vdec_p0_composite", + dec_parent_names, ARRAY_SIZE(dec_parent_names), + &vdec_p0_mux.hw, &vdec_p0_div.hw, + &vdec_p0_gate.hw, 0 + }, + + {CLKID_VDEC_P1_COMP, "vdec_p1_composite", + dec_parent_names, ARRAY_SIZE(dec_parent_names), + &vdec_p1_mux.hw, &vdec_p1_div.hw, + &vdec_p1_gate.hw, 0 + }, + + {CLKID_HCODEC_P0_COMP, "hcodec_p0_composite", + dec_parent_names, ARRAY_SIZE(dec_parent_names), + &hcodec_p0_mux.hw, &hcodec_p0_div.hw, + &hcodec_p0_gate.hw, 0 + }, + + {CLKID_HCODEC_P1_COMP, "hcodec_p1_composite", + dec_parent_names, ARRAY_SIZE(dec_parent_names), + &hcodec_p1_mux.hw, &hcodec_p1_div.hw, + &hcodec_p1_gate.hw, 0 + }, + + {CLKID_HEVC_P0_COMP, "hevc_p0_composite", + dec_parent_names, ARRAY_SIZE(dec_parent_names), + &hevc_p0_mux.hw, &hevc_p0_div.hw, + &hevc_p0_gate.hw, 0 + }, + + {CLKID_HEVC_P1_COMP, "hevc_p1_composite", + dec_parent_names, ARRAY_SIZE(dec_parent_names), + &hevc_p1_mux.hw, &hevc_p1_div.hw, + &hevc_p1_gate.hw, 0 + }, + + {CLKID_AMCLK_COMP, "cts_amclk_composite", + cts_amclk_parent_names, ARRAY_SIZE(cts_amclk_parent_names), + &cts_amclk_mux.hw, &cts_amclk_div.hw, + &cts_amclk_gate.hw, 0 + },/* cts_amclk in clktress doc*/ + + {CLKID_IEC958_INT_COMP, "iec958_int_composite", + cts_iec958_int_parent_names, ARRAY_SIZE(cts_iec958_int_parent_names), + &cts_iec958_int_mux.hw, &cts_iec958_int_div.hw, + &cts_iec958_int_gate.hw, 0 + }, + + {CLKID_PDM_COMP, "cts_pdm_composite", + cts_pdm_parent_names, ARRAY_SIZE(cts_pdm_parent_names), + &cts_pdm_mux.hw, &cts_pdm_div.hw, + &cts_pdm_gate.hw, 0 + },/* cts_pdm in clktrees doc */ + + {CLKID_AUDIN_MCLK_COMP, "cts_audin_mclk_composite", + cts_audin_mclk_parent_names, ARRAY_SIZE(cts_audin_mclk_parent_names), + &cts_audin_mclk_mux.hw, &cts_audin_mclk_div.hw, + &cts_audin_mclk_gate.hw, 0 + },/* cts_audin_mclk in clktrees doc */ + + {CLKID_AUDIN_SCLK_COMP, "cts_audin_sclk_composite", + cts_audin_sclk_parent_names, ARRAY_SIZE(cts_audin_sclk_parent_names), + NULL, &cts_audin_sclk_div.hw, &cts_audin_sclk_gate.hw, 0 + },/* cts_audin_sclk in clktrees doc */ + + {CLKID_AUDIN_LRCLK_COMP, "cts_audin_lrclk_composite", + cts_audin_lrclk_parent_names, ARRAY_SIZE(cts_audin_lrclk_parent_names), + NULL, &cts_audin_lrclk_div.hw, &cts_audin_lrclk_gate.hw, 0 + },/* cts_audin_lrclk in clktrees doc */ + + {CLKID_ALOCKER_IN_COMP, "cts_alocker_in_composite", + cts_alocker_in_parent_names, ARRAY_SIZE(cts_alocker_in_parent_names), + &cts_alocker_in_mux.hw, &cts_alocker_in_div.hw, + &cts_alocker_in_gate.hw, 0 + },/* cts_alocker_in_clk in clktrees doc */ + + {CLKID_ALOCKER_OUT_COMP, "cts_alocker_out_composite", + cts_alocker_out_parent_names, ARRAY_SIZE(cts_alocker_out_parent_names), + &cts_alocker_out_mux.hw, &cts_alocker_out_div.hw, + &cts_alocker_out_gate.hw, 0 + },/* cts_alocker_out_clk in clktrees doc */ + + {CLKID_PCM_MCLK_COMP, "cts_pcm_mclk_composite", + cts_pcm_mclk_parent_names, ARRAY_SIZE(cts_pcm_mclk_parent_names), + &cts_pcm_mclk_mux.hw, &cts_pcm_mclk_div.hw, + &cts_pcm_mclk_gate.hw, 0 + },/* cts_pcm_mclk in clktrees doc */ + + {CLKID_PCM_SCLK_COMP, "cts_pcm_sclk_composite", + cts_pcm_sclk_parent_names, ARRAY_SIZE(cts_pcm_sclk_parent_names), + NULL, &cts_pcm_sclk_div.hw, &cts_pcm_sclk_gate.hw, 0 + },/* cts_pcm_sclk in clktrees doc */ + + {CLKID_CTS_DEMOD_COMP, "cts_demod_composite", + cts_demod_parent_names, ARRAY_SIZE(cts_demod_parent_names), + &cts_demod_mux.hw, &cts_demod_div.hw, + &cts_demod_gate.hw, 0 + },/* cts vid lock clock in clktrees doc */ + + {CLKID_ADC_EXTCLK_IN_COMP, "adc_extclk_composite", + adc_extclk_in_parent_names, ARRAY_SIZE(adc_extclk_in_parent_names), + &adc_extclk_in_mux.hw, &adc_extclk_in_div.hw, + &adc_extclk_in_gate.hw, 0 + },/* cts adc extclk clock in clktrees doc */ + + {CLKID_VID_LOCK_COMP, "vid_lock_composite", + cts_vid_lock_parent_names, ARRAY_SIZE(cts_vid_lock_parent_names), + &cts_vid_lock_mux.hw, &cts_vid_lock_div.hw, + &cts_vid_lock_gate.hw, 0 + },/* vid lock in clktrees doc */ + + {CLKID_CTS_ATV_DMD_COMP, "cts_atv_dmd_composite", + cts_atv_dmd_parent_names, ARRAY_SIZE(cts_atv_dmd_parent_names), + &cts_atv_dmd_mux.hw, &cts_atv_dmd_div.hw, + &cts_atv_dmd_gate.hw, 0 + },/* vid lock in clktrees doc */ + + {CLKID_ALT_32K_COMP, "alt_32k_composite", + alt_32k_parent_names, ARRAY_SIZE(alt_32k_parent_names), + &alt_32k_mux.hw, &alt_32k_div.hw, + &alt_32k_gate.hw, 0 + },/* alt 32k in clktrees doc */ +}; + +/* array for single hw*/ +static struct meson_hw m_hw[] = { + {CLKID_VDEC_MUX, &vdec_mux.hw}, + {CLKID_HCODEC_MUX, &hcodec_mux.hw}, + {CLKID_HEVC_MUX, &hevc_mux.hw}, +}; +void meson_txl_media_init(void) +{ + int i; + int length, lengthhw; + + length = ARRAY_SIZE(m_composite); + lengthhw = ARRAY_SIZE(m_hw); + + /* Populate base address for media muxes */ + for (i = 0; i < ARRAY_SIZE(txl_media_clk_muxes); i++) + txl_media_clk_muxes[i]->reg = clk_base + + (u64)txl_media_clk_muxes[i]->reg; + + /* Populate base address for media divs */ + for (i = 0; i < ARRAY_SIZE(txl_media_clk_divs); i++) + txl_media_clk_divs[i]->reg = clk_base + + (u64)txl_media_clk_divs[i]->reg; + + /* Populate base address for media gates */ + for (i = 0; i < ARRAY_SIZE(txl_media_clk_gates); i++) + txl_media_clk_gates[i]->reg = clk_base + + (u64)txl_media_clk_gates[i]->reg; + + meson_clk_register_composite(clks, m_composite, length); + + clks[CLKID_VPU_MUX] = clk_register(NULL, &vpu_mux.hw); + WARN_ON(IS_ERR(clks[CLKID_VPU_MUX])); + clk_prepare_enable(clks[CLKID_VPU_MUX]); + + clks[CLKID_VAPB_MUX] = clk_register(NULL, &vapb_mux.hw); + WARN_ON(IS_ERR(clks[CLKID_VAPB_MUX])); + clk_prepare_enable(clks[CLKID_VAPB_MUX]); + + clks[CLKID_GE2D_GATE] = clk_register(NULL, &ge2d_gate.hw); + WARN_ON(IS_ERR(clks[CLKID_GE2D_GATE])); + + /*mux*/ + clks[CLKID_VDEC_MUX] = clk_register(NULL, &vdec_mux.hw); + WARN_ON(IS_ERR(clks[CLKID_VDEC_MUX])); + + clks[CLKID_HCODEC_MUX] = clk_register(NULL, &hcodec_mux.hw); + WARN_ON(IS_ERR(clks[CLKID_HCODEC_MUX])); + + clks[CLKID_HEVC_MUX] = clk_register(NULL, &hevc_mux.hw); + WARN_ON(IS_ERR(clks[CLKID_HEVC_MUX])); + + clks[CLKID_IEC958_MUX] = clk_register(NULL, &cts_iec958_spdif.hw); + WARN_ON(IS_ERR(clks[CLKID_IEC958_MUX])); + /* todo: set default div4 parent for tmp clkb */ + clk_set_parent(clks[CLKID_VPU_CLKB_TMP_COMP], clks[CLKID_FCLK_DIV4]); +} diff --git a/drivers/amlogic/clk/txl/txl_clk_sdemmc.c b/drivers/amlogic/clk/txl/txl_clk_sdemmc.c new file mode 100644 index 0000000..5aff710 --- /dev/null +++ b/drivers/amlogic/clk/txl/txl_clk_sdemmc.c @@ -0,0 +1,90 @@ +/* + * drivers/amlogic/clk/txl/txl_clk_sdemmc.c + * + * Copyright (C) 2018 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "../clkc.h" +#include "txl.h" + +PNAME(sd_emmc_parent_names) = { "xtal", "fclk_div2", + "fclk_div3", "fclk_div5", "fclk_div7", "mpll2", "mpll3", "gp0" }; +/*sd_emmc A*/ +static MUX(sd_emmc_p0_mux_A, HHI_SD_EMMC_CLK_CNTL, 0x7, 9, +sd_emmc_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(sd_emmc_p0_div_A, HHI_SD_EMMC_CLK_CNTL, 0, 7, "sd_emmc_p0_mux_A", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(sd_emmc_p0_gate_A, HHI_SD_EMMC_CLK_CNTL, 7, "sd_emmc_p0_div_A", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +/*sd_emmc B*/ +static MUX(sd_emmc_p0_mux_B, HHI_SD_EMMC_CLK_CNTL, 0x7, 25, +sd_emmc_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(sd_emmc_p0_div_B, HHI_SD_EMMC_CLK_CNTL, 16, 7, "sd_emmc_p0_mux_B", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(sd_emmc_p0_gate_B, HHI_SD_EMMC_CLK_CNTL, 23, "sd_emmc_p0_div_B", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); + +/*sd_emmc C*/ +static MUX(sd_emmc_p0_mux_C, HHI_NAND_CLK_CNTL, 0x7, 9, +sd_emmc_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static DIV(sd_emmc_p0_div_C, HHI_NAND_CLK_CNTL, 0, 7, "sd_emmc_p0_mux_C", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); +static GATE(sd_emmc_p0_gate_C, HHI_NAND_CLK_CNTL, 7, "sd_emmc_p0_div_C", + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); + +static struct meson_composite sdemmc_comp[] = { + {CLKID_SD_EMMC_A_COMP, "sd_emmc_p0_A_comp", + sd_emmc_parent_names, ARRAY_SIZE(sd_emmc_parent_names), + &sd_emmc_p0_mux_A.hw, &sd_emmc_p0_div_A.hw, + &sd_emmc_p0_gate_A.hw, 0 + },/* sd_emmc_A */ + + {CLKID_SD_EMMC_B_COMP, "sd_emmc_p0_B_comp", + sd_emmc_parent_names, ARRAY_SIZE(sd_emmc_parent_names), + &sd_emmc_p0_mux_B.hw, &sd_emmc_p0_div_B.hw, + &sd_emmc_p0_gate_B.hw, 0 + },/* sd_emmc_B */ + + {CLKID_SD_EMMC_C_COMP, "sd_emmc_p0_C_comp", + sd_emmc_parent_names, ARRAY_SIZE(sd_emmc_parent_names), + &sd_emmc_p0_mux_C.hw, &sd_emmc_p0_div_C.hw, + &sd_emmc_p0_gate_C.hw, 0 + },/* sd_emmc_C */ +}; + +void meson_txl_sdemmc_init(void) +{ + int length = ARRAY_SIZE(sdemmc_comp); + + /* Populate base address for reg */ + sd_emmc_p0_mux_A.reg = clk_base + (u64)(sd_emmc_p0_mux_A.reg); + sd_emmc_p0_div_A.reg = clk_base + (u64)(sd_emmc_p0_div_A.reg); + sd_emmc_p0_gate_A.reg = clk_base + (u64)(sd_emmc_p0_gate_A.reg); + sd_emmc_p0_mux_B.reg = clk_base + (u64)(sd_emmc_p0_mux_B.reg); + sd_emmc_p0_div_B.reg = clk_base + (u64)(sd_emmc_p0_div_B.reg); + sd_emmc_p0_gate_B.reg = clk_base + (u64)(sd_emmc_p0_gate_B.reg); + sd_emmc_p0_mux_C.reg = clk_base + (u64)(sd_emmc_p0_mux_C.reg); + sd_emmc_p0_div_C.reg = clk_base + (u64)(sd_emmc_p0_div_C.reg); + sd_emmc_p0_gate_C.reg = clk_base + (u64)(sd_emmc_p0_gate_C.reg); + + meson_clk_register_composite(clks, sdemmc_comp, length); +} diff --git a/include/dt-bindings/clock/amlogic,txl-clkc.h b/include/dt-bindings/clock/amlogic,txl-clkc.h new file mode 100644 index 0000000..964110e --- /dev/null +++ b/include/dt-bindings/clock/amlogic,txl-clkc.h @@ -0,0 +1,269 @@ +/* + * include/dt-bindings/clock/txl-clkc.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef __TXL_CLKC_H +#define __TXL_CLKC_H + +/* + * CLKID index values + */ +#define CLKID_SYS_PLL 0 +#define CLKID_FIXED_PLL 1 +#define CLKID_FCLK_DIV2 2 +#define CLKID_FCLK_DIV3 3 +#define CLKID_FCLK_DIV4 4 +#define CLKID_FCLK_DIV5 5 +#define CLKID_FCLK_DIV7 6 +#define CLKID_GP0_PLL 7 +#define CLKID_GP1_PLL 8 +#define CLKID_MPEG_SEL 9 +#define CLKID_MPEG_DIV 10 +#define CLKID_CLK81 11 +#define CLKID_MPLL0 12 +#define CLKID_MPLL1 13 +#define CLKID_MPLL2 14 +#define CLKID_MPLL3 15 +#define CLKID_CPU_FCLK_P00 16 +#define CLKID_CPU_FCLK_P01 17 +#define CLKID_CPU_FCLK_P0 18 +#define CLKID_CPU_FCLK_P10 19 +#define CLKID_CPU_FCLK_P11 20 +#define CLKID_CPU_FCLK_P1 21 +#define CLKID_CPU_FCLK_P 22 +#define CLKID_CPU_CLK 23 +/*#define CLKID_ADC_PLL 24*/ + +/*HHI_GCLK_MPEG0: 0x50*/ +#define GATE_BASE0 (25 - 1) + +#define CLKID_DDR (GATE_BASE0 + 0) +#define CLKID_DOS (GATE_BASE0 + 1) +#define CLKID_ISA (GATE_BASE0 + 2) +#define CLKID_PL301 (GATE_BASE0 + 3) +#define CLKID_PERIPHS (GATE_BASE0 + 4) +#define CLKID_SPICC0 (GATE_BASE0 + 5) +#define CLKID_I2C (GATE_BASE0 + 6) +#define CLKID_SANA (GATE_BASE0 + 7) +#define CLKID_SMART_CARD (GATE_BASE0 + 8) +#define CLKID_RNG0 (GATE_BASE0 + 9) +#define CLKID_UART0 (GATE_BASE0 + 10) +#define CLKID_ASYNC_FIFO (GATE_BASE0 + 11) +#define CLKID_HIU_REG (GATE_BASE0 + 12) +#define CLKID_HDMIRX_APB (GATE_BASE0 + 13) +#define CLKID_ASSIST_MISC (GATE_BASE0 + 14) +#define CLKID_SD_EMMC_B (GATE_BASE0 + 15) +#define CLKID_SD_EMMC_C (GATE_BASE0 + 16) +#define CLKID_DMA (GATE_BASE0 + 17) +#define CLKID_ACODEC (GATE_BASE0 + 18) +#define CLKID_ATV_DEMOD (GATE_BASE0 + 19) +#define CLKID_SPI (GATE_BASE0 + 20) +#define CLKID_ADEC (GATE_BASE0 + 21) + +/*HHI_GCLK_MPEG1: 0x51*/ +#define GATE_BASE1 (GATE_BASE0 + 22) + +#define CLKID_PCLK_TVFE (GATE_BASE1 + 0) +#define CLKID_I2S_SPDIF (GATE_BASE1 + 1) +#define CLKID_ETH_CORE (GATE_BASE1 + 2) +#define CLKID_DEMUX (GATE_BASE1 + 3) +#define CLKID_AIU_GLUE (GATE_BASE1 + 4) +#define CLKID_IEC958 (GATE_BASE1 + 5) +#define CLKID_I2S_OUT (GATE_BASE1 + 6) +#define CLKID_AMCLK_MEASURE (GATE_BASE1 + 7) +#define CLKID_AIFIFO2 (GATE_BASE1 + 8) +#define CLKID_MIXER (GATE_BASE1 + 9) +#define CLKID_MIXER_IFACE (GATE_BASE1 + 10) +#define CLKID_ADC (GATE_BASE1 + 11) +#define CLKID_AIU_TOP (GATE_BASE1 + 12) +#define CLKID_UART1 (GATE_BASE1 + 13) +#define CLKID_USB0 (GATE_BASE1 + 14) +#define CLKID_USB1 (GATE_BASE1 + 15) +#define CLKID_G2D (GATE_BASE1 + 16) +#define CLKID_RESET (GATE_BASE1 + 17) +#define CLKID_DOS_PARSER (GATE_BASE1 + 18) +#define CLKID_USB_GENERAL (GATE_BASE1 + 19) +#define CLKID_AHB_ARB0 (GATE_BASE1 + 20) +#define CLKID_EFUSE (GATE_BASE1 + 21) +#define CLKID_BOOT_ROM (GATE_BASE1 + 22) + +/*HHI_GCLK_MPEG2: 0x52*/ +#define GATE_BASE2 (GATE_BASE1 + 23) + +#define CLKID_AHB_DATA_BUS (GATE_BASE2 + 0) +#define CLKID_AHB_CTRL_BUS (GATE_BASE2 + 1) +#define CLKID_USB1_TO_DDR (GATE_BASE2 + 2) +#define CLKID_USB0_TO_DDR (GATE_BASE2 + 3) +#define CLKID_AIU_PCLK (GATE_BASE2 + 4) +#define CLKID_MMC_PCLK (GATE_BASE2 + 5) +#define CLKID_HDMI_HDCP22 (GATE_BASE2 + 6) +#define CLKID_UART2 (GATE_BASE2 + 7) +#define CLKID_UART3 (GATE_BASE2 + 9) +#define CLKID_VPU_INTR (GATE_BASE2 + 9) +#define CLKID_SEC_AHB_AHB3_BRIDGE (GATE_BASE2 + 10) +#define CLKID_DEMOD_TVFE (GATE_BASE2 + 11) +#define CLKID_GIC (GATE_BASE2 + 12) + +/*HHI_GCLK_OTHER: 0x55*/ +#define GATE_OTHER (GATE_BASE2 + 13) + +#define CLKID_VCLK2_VENCI0 (GATE_OTHER + 0) +#define CLKID_VCLK2_VENCI1 (GATE_OTHER + 1) +#define CLKID_VCLK2_VENCP0 (GATE_OTHER + 2) +#define CLKID_VCLK2_VENCP1 (GATE_OTHER + 3) +#define CLKID_VCLK2_VENCT0 (GATE_OTHER + 4) +#define CLKID_VCLK2_VENCT1 (GATE_OTHER + 5) +#define CLKID_VCLK2_OTHER (GATE_OTHER + 6) +#define CLKID_VCLK2_ENCI (GATE_OTHER + 7) +#define CLKID_VCLK2_ENCP (GATE_OTHER + 8) +#define CLKID_DAC_CLK (GATE_OTHER + 9) +#define CLKID_AOCLK_GATE (GATE_OTHER + 10) +#define CLKID_IEC958_GATE (GATE_OTHER + 11) +#define CLKID_ENC480P (GATE_OTHER + 12) +#define CLKID_RNG1 (GATE_OTHER + 13) +#define CLKID_VCLK2_ENCT (GATE_OTHER + 14) +#define CLKID_VCLK2_ENCL (GATE_OTHER + 15) +#define CLKID_VCLK2_VENCLMMC (GATE_OTHER + 16) +#define CLKID_VCLK2_VENCL (GATE_OTHER + 17) +#define CLKID_VCLK2_OTHER1 (GATE_OTHER + 18) + +/*HHI_GCLK_OTHER: 0x55*/ +/*above: 25+25+21+12+19*/ +#define GATE_AO_BASE (GATE_OTHER + 19) + +#define CLKID_AO_MEDIA_CPU (GATE_AO_BASE + 0) +#define CLKID_AO_AHB_SRAM (GATE_AO_BASE + 1) +#define CLKID_AO_AHB_BUS (GATE_AO_BASE + 2) +#define CLKID_AO_IFACE (GATE_AO_BASE + 3) +#define CLKID_AO_I2C (GATE_AO_BASE + 4) + +/*above: 25+25+21+12+19+5=107*/ +#define CLOCK_GATE (GATE_AO_BASE + 5) + +#define CLKID_SD_EMMC_A_COMP (CLOCK_GATE + 0) +#define CLKID_SD_EMMC_B_COMP (CLOCK_GATE + 1) +#define CLKID_SD_EMMC_C_COMP (CLOCK_GATE + 2) + +/*above: 25+25+21+12+19+5+16*/ +#define CLKID_MEDIA_BASE (CLOCK_GATE + 3) + +#define CLKID_VPU_P0_MUX (CLKID_MEDIA_BASE + 0) +#define CLKID_VPU_P0_DIV (CLKID_MEDIA_BASE + 1) +#define CLKID_VPU_P0_GATE (CLKID_MEDIA_BASE + 2) +#define CLKID_VPU_P0_COMP (CLKID_MEDIA_BASE + 3) +#define CLKID_VPU_P1_MUX (CLKID_MEDIA_BASE + 4) +#define CLKID_VPU_P1_DIV (CLKID_MEDIA_BASE + 5) +#define CLKID_VPU_P1_GATE (CLKID_MEDIA_BASE + 6) +#define CLKID_VPU_P1_COMP (CLKID_MEDIA_BASE + 7) +#define CLKID_VPU_MUX (CLKID_MEDIA_BASE + 8) +#define CLKID_VAPB_P0_MUX (CLKID_MEDIA_BASE + 9) +#define CLKID_VAPB_P0_DIV (CLKID_MEDIA_BASE + 10) +#define CLKID_VAPB_P0_GATE (CLKID_MEDIA_BASE + 11) +#define CLKID_VAPB_P0_COMP (CLKID_MEDIA_BASE + 12) +#define CLKID_VAPB_P1_MUX (CLKID_MEDIA_BASE + 13) +#define CLKID_VAPB_P1_DIV (CLKID_MEDIA_BASE + 14) +#define CLKID_VAPB_P1_GATE (CLKID_MEDIA_BASE + 15) +#define CLKID_VAPB_P1_COMP (CLKID_MEDIA_BASE + 16) +#define CLKID_VAPB_MUX (CLKID_MEDIA_BASE + 17) +#define CLKID_GE2D_GATE (CLKID_MEDIA_BASE + 18) +#define CLKID_VDIN_MEAS_MUX (CLKID_MEDIA_BASE + 19) +#define CLKID_VDIN_MEAS_DIV (CLKID_MEDIA_BASE + 20) +#define CLKID_VDIN_MEAS_GATE (CLKID_MEDIA_BASE + 21) +#define CLKID_VDIN_MEAS_COMP (CLKID_MEDIA_BASE + 22) + +#define CLKID_VPU_CLKB_TMP_MUX (CLKID_MEDIA_BASE + 23) +#define CLKID_VPU_CLKB_TMP_DIV (CLKID_MEDIA_BASE + 24) +#define CLKID_VPU_CLKB_TMP_GATE (CLKID_MEDIA_BASE + 25) +#define CLKID_VPU_CLKB_DIV (CLKID_MEDIA_BASE + 26) +#define CLKID_VPU_CLKB_GATE (CLKID_MEDIA_BASE + 27) +#define CLKID_VPU_CLKB_TMP_COMP (CLKID_MEDIA_BASE + 28) +#define CLKID_VPU_CLKB_COMP (CLKID_MEDIA_BASE + 29) +#define CLKID_CTS_DEMOD_COMP (CLKID_MEDIA_BASE + 30) +#define CLKID_ADC_EXTCLK_IN_COMP (CLKID_MEDIA_BASE + 31) +#define CLKID_VID_LOCK_COMP (CLKID_MEDIA_BASE + 32) +#define CLKID_CTS_ATV_DMD_COMP (CLKID_MEDIA_BASE + 33) +#define CLKID_ALT_32K_COMP (CLKID_MEDIA_BASE + 34) + +#define CLKID_HDMIRX_BASE (CLKID_MEDIA_BASE + 35) + +#define CLKID_HDMIRX_CFG_COMP (CLKID_HDMIRX_BASE + 0) +#define CLKID_HDMIRX_MODET_COMP (CLKID_HDMIRX_BASE + 1) +#define CLKID_HDMIRX_AUDMEAS_COMP (CLKID_HDMIRX_BASE + 2) +#define CLKID_HDMIRX_ACR_COMP (CLKID_HDMIRX_BASE + 3) +#define CLKID_HDCP22_SKP_COMP (CLKID_HDMIRX_BASE + 4) +#define CLKID_HDCP22_ESM_COMP (CLKID_HDMIRX_BASE + 5) + +#define CLKID_VHDEC_BASE (CLKID_HDMIRX_BASE + 6) + +#define CLKID_VDEC_P0_MUX (CLKID_VHDEC_BASE + 0) +#define CLKID_VDEC_P0_DIV (CLKID_VHDEC_BASE + 1) +#define CLKID_VDEC_P0_GATE (CLKID_VHDEC_BASE + 2) +#define CLKID_VDEC_P0_COMP (CLKID_VHDEC_BASE + 3) +#define CLKID_VDEC_P1_MUX (CLKID_VHDEC_BASE + 4) +#define CLKID_VDEC_P1_DIV (CLKID_VHDEC_BASE + 5) +#define CLKID_VDEC_P1_GATE (CLKID_VHDEC_BASE + 6) +#define CLKID_VDEC_P1_COMP (CLKID_VHDEC_BASE + 7) +#define CLKID_HCODEC_P0_MUX (CLKID_VHDEC_BASE + 8) +#define CLKID_HCODEC_P0_DIV (CLKID_VHDEC_BASE + 9) +#define CLKID_HCODEC_P0_GATE (CLKID_VHDEC_BASE + 10) +#define CLKID_HCODEC_P0_COMP (CLKID_VHDEC_BASE + 11) +#define CLKID_HCODEC_P1_MUX (CLKID_VHDEC_BASE + 12) +#define CLKID_HCODEC_P1_DIV (CLKID_VHDEC_BASE + 13) +#define CLKID_HCODEC_P1_GATE (CLKID_VHDEC_BASE + 14) +#define CLKID_HCODEC_P1_COMP (CLKID_VHDEC_BASE + 15) +#define CLKID_HEVC_P0_MUX (CLKID_VHDEC_BASE + 16) +#define CLKID_HEVC_P0_DIV (CLKID_VHDEC_BASE + 17) +#define CLKID_HEVC_P0_GATE (CLKID_VHDEC_BASE + 18) +#define CLKID_HEVC_P0_COMP (CLKID_VHDEC_BASE + 19) +#define CLKID_HEVC_P1_MUX (CLKID_VHDEC_BASE + 20) +#define CLKID_HEVC_P1_DIV (CLKID_VHDEC_BASE + 21) +#define CLKID_HEVC_P1_GATE (CLKID_VHDEC_BASE + 22) +#define CLKID_HEVC_P1_COMP (CLKID_VHDEC_BASE + 23) +#define CLKID_VDEC_MUX (CLKID_VHDEC_BASE + 24) +#define CLKID_HCODEC_MUX (CLKID_VHDEC_BASE + 25) +#define CLKID_HEVC_MUX (CLKID_VHDEC_BASE + 26) + +#define CLKID_AUDIO_BASE (CLKID_VHDEC_BASE + 27) + +#define CLKID_AMCLK_COMP (CLKID_AUDIO_BASE + 0) +#define CLKID_IEC958_INT_COMP (CLKID_AUDIO_BASE + 1) +#define CLKID_IEC958_MUX (CLKID_AUDIO_BASE + 2) +#define CLKID_PDM_COMP (CLKID_AUDIO_BASE + 3) +#define CLKID_AUDIN_MCLK_COMP (CLKID_AUDIO_BASE + 4) +#define CLKID_AUDIN_SCLK_COMP (CLKID_AUDIO_BASE + 5) +#define CLKID_AUDIN_LRCLK_COMP (CLKID_AUDIO_BASE + 6) +#define CLKID_ALOCKER_IN_COMP (CLKID_AUDIO_BASE + 7) +#define CLKID_ALOCKER_OUT_COMP (CLKID_AUDIO_BASE + 8) +#define CLKID_PCM_MCLK_COMP (CLKID_AUDIO_BASE + 9) +#define CLKID_PCM_SCLK_COMP (CLKID_AUDIO_BASE + 10) + +#define CLKID_GPU_BASE (CLKID_AUDIO_BASE + 11) + +#define CLKID_GPU_P0_COMP (CLKID_GPU_BASE + 0) +#define CLKID_GPU_P1_COMP (CLKID_GPU_BASE + 1) +#define CLKID_GPU_MUX (CLKID_GPU_BASE + 2) + +/*above: 25+25+21+12+19+5+16+30*/ +#define CLKID_AO_BASE (CLKID_GPU_BASE + 3) +#define CLKID_AO_CLK81 (CLKID_AO_BASE + 0) +#define CLKID_SARADC_MUX (CLKID_AO_BASE + 1) +#define CLKID_SARADC_DIV (CLKID_AO_BASE + 2) +#define CLKID_SARADC_GATE (CLKID_AO_BASE + 3) + +/*above: 25+25+21+12+19+5+16+30+6+4 +27 +11 +3=204*/ + +#define NR_CLKS (CLKID_AO_BASE + 4) +#endif /* __TXL_CLKC_H */ -- 2.7.4