From a4ebc835cbcbc0a6f55f1dbe68332cfd8359fdfd Mon Sep 17 00:00:00 2001 From: Alan Modra Date: Fri, 18 May 2012 00:39:28 +0000 Subject: [PATCH] * ppc-opc.c (powerpc_macros): Add entries for e_extlwi to e_clrlslwi. --- opcodes/ChangeLog | 4 ++++ opcodes/ppc-opc.c | 12 ++++++++++++ 2 files changed, 16 insertions(+) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 05b792a..544eed2 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,9 @@ 2012-05-17 James Lemke + * ppc-opc.c (powerpc_macros): Add entries for e_extlwi to e_clrlslwi. + +2012-05-17 James Lemke + * ppc-opc.c (extract_sprg): Use ALLOW8_SPRG to include VLE. 2012-05-17 Daniel Richard G. diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 74fba68..a1c9963 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -6450,6 +6450,18 @@ const struct powerpc_macro powerpc_macros[] = { {"clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"}, {"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"}, {"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"}, + +{"e_extlwi", 4, PPCVLE, "e_rlwinm %0,%1,%3,0,(%2)-1"}, +{"e_extrwi", 4, PPCVLE, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"}, +{"e_inslwi", 4, PPCVLE, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, +{"e_insrwi", 4, PPCVLE, "e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, +{"e_rotlwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31"}, +{"e_rotrwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"}, +{"e_slwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31-(%2)"}, +{"e_srwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, +{"e_clrlwi", 3, PPCVLE, "e_rlwinm %0,%1,0,%2,31"}, +{"e_clrrwi", 3, PPCVLE, "e_rlwinm %0,%1,0,0,31-(%2)"}, +{"e_clrlslwi",4, PPCVLE, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"}, }; const int powerpc_num_macros = -- 2.7.4