From a4b039db04c26e4c35db4a6dfc56552661f1ea0c Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 30 Mar 2017 07:53:24 +0100 Subject: [PATCH] radv: add tess shader stage user data support. This just adds support for tess to the shader stage conversion and emits the per-stage descriptors/constants for tess stages. Reviewed-by: Bas Nieuwenhuizen Signed-off-by: Dave Airlie --- src/amd/vulkan/radv_cmd_buffer.c | 45 +++++++++++++++++++++++++++++++++------- 1 file changed, 38 insertions(+), 7 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index e502452..e066704 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -376,17 +376,27 @@ static unsigned radv_pack_float_12p4(float x) } static uint32_t -shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs) +shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs, bool has_tess) { switch (stage) { case MESA_SHADER_FRAGMENT: return R_00B030_SPI_SHADER_USER_DATA_PS_0; case MESA_SHADER_VERTEX: - return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0; + if (has_tess) + return R_00B530_SPI_SHADER_USER_DATA_LS_0; + else + return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0; case MESA_SHADER_GEOMETRY: return R_00B230_SPI_SHADER_USER_DATA_GS_0; case MESA_SHADER_COMPUTE: return R_00B900_COMPUTE_USER_DATA_0; + case MESA_SHADER_TESS_CTRL: + return R_00B430_SPI_SHADER_USER_DATA_HS_0; + case MESA_SHADER_TESS_EVAL: + if (has_gs) + return R_00B330_SPI_SHADER_USER_DATA_ES_0; + else + return R_00B130_SPI_SHADER_USER_DATA_VS_0; default: unreachable("unknown shader"); } @@ -407,7 +417,7 @@ radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer, int idx, uint64_t va) { struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx); - uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline)); + uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline)); if (loc->sgpr_idx == -1) return; assert(loc->num_sgprs == 2); @@ -1112,7 +1122,7 @@ emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer, gl_shader_stage stage) { struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx]; - uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline)); + uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline)); if (desc_set_loc->sgpr_idx == -1) return; @@ -1147,6 +1157,16 @@ radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer, idx, set->va, MESA_SHADER_GEOMETRY); + if ((stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) && radv_pipeline_has_tess(pipeline)) + emit_stage_descriptor_set_userdata(cmd_buffer, pipeline, + idx, set->va, + MESA_SHADER_TESS_CTRL); + + if ((stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) && radv_pipeline_has_tess(pipeline)) + emit_stage_descriptor_set_userdata(cmd_buffer, pipeline, + idx, set->va, + MESA_SHADER_TESS_EVAL); + if (stages & VK_SHADER_STAGE_COMPUTE_BIT) emit_stage_descriptor_set_userdata(cmd_buffer, pipeline, idx, set->va, @@ -1212,6 +1232,14 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer, radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_GEOMETRY, AC_UD_PUSH_CONSTANTS, va); + if ((stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) && radv_pipeline_has_tess(pipeline)) + radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_TESS_CTRL, + AC_UD_PUSH_CONSTANTS, va); + + if ((stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) && radv_pipeline_has_tess(pipeline)) + radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_TESS_EVAL, + AC_UD_PUSH_CONSTANTS, va); + if (stages & VK_SHADER_STAGE_COMPUTE_BIT) radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_COMPUTE, AC_UD_PUSH_CONSTANTS, va); @@ -2200,7 +2228,8 @@ void radv_CmdDraw( struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX, AC_UD_VS_BASE_VERTEX_START_INSTANCE); if (loc->sgpr_idx != -1) { - uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline)); + uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline), + radv_pipeline_has_tess(cmd_buffer->state.pipeline)); radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 3); radeon_emit(cmd_buffer->cs, firstVertex); radeon_emit(cmd_buffer->cs, firstInstance); @@ -2255,7 +2284,8 @@ void radv_CmdDrawIndexed( struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX, AC_UD_VS_BASE_VERTEX_START_INSTANCE); if (loc->sgpr_idx != -1) { - uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline)); + uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline), + radv_pipeline_has_tess(cmd_buffer->state.pipeline)); radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 3); radeon_emit(cmd_buffer->cs, vertexOffset); radeon_emit(cmd_buffer->cs, firstInstance); @@ -2308,7 +2338,8 @@ radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer, struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX, AC_UD_VS_BASE_VERTEX_START_INSTANCE); - uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline)); + uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline), + radv_pipeline_has_tess(cmd_buffer->state.pipeline)); assert(loc->sgpr_idx != -1); radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0)); radeon_emit(cs, 1); -- 2.7.4