From a48b8660680722be531d073d0abab3f2c07d1699 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 23 Apr 2015 23:34:48 +0000 Subject: [PATCH] R600/SI: Special case v_mov_b32 as really rematerializable This should be fixed to properly understand all rematerializable instructions while ignoring implicit reads of exec. llvm-svn: 235671 --- llvm/lib/Target/R600/SIInstrInfo.cpp | 14 ++++++++++++++ llvm/lib/Target/R600/SIInstrInfo.h | 3 +++ 2 files changed, 17 insertions(+) diff --git a/llvm/lib/Target/R600/SIInstrInfo.cpp b/llvm/lib/Target/R600/SIInstrInfo.cpp index ba98ad7..6617075 100644 --- a/llvm/lib/Target/R600/SIInstrInfo.cpp +++ b/llvm/lib/Target/R600/SIInstrInfo.cpp @@ -74,6 +74,20 @@ static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) { return N0->getOperand(Op0Idx) == N1->getOperand(Op1Idx); } +bool SIInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI, + AliasAnalysis *AA) const { + // TODO: The generic check fails for VALU instructions that should be + // rematerializable due to implicit reads of exec. We really want all of the + // generic logic for this except for this. + switch (MI->getOpcode()) { + case AMDGPU::V_MOV_B32_e32: + case AMDGPU::V_MOV_B32_e64: + return true; + default: + return false; + } +} + bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1, int64_t &Offset0, int64_t &Offset1) const { diff --git a/llvm/lib/Target/R600/SIInstrInfo.h b/llvm/lib/Target/R600/SIInstrInfo.h index a9aa99f..7e049dc 100644 --- a/llvm/lib/Target/R600/SIInstrInfo.h +++ b/llvm/lib/Target/R600/SIInstrInfo.h @@ -72,6 +72,9 @@ public: return RI; } + bool isReallyTriviallyReMaterializable(const MachineInstr *MI, + AliasAnalysis *AA) const override; + bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override; -- 2.7.4