From a487928908226df493a3ce145ecf4bb39296714e Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Thu, 13 Oct 2011 10:08:34 -0700 Subject: [PATCH] drm/i915: remove transcoder PLL mashing from mode_set per specs Belongs in PCH enable instead. The duplication is worrying and the specs explicitly list transcoder select *after* actual PLL enable, which doesn't occur until later. Signed-off-by: Jesse Barnes Tested-By: Eugeni Dodonov Reviewed-By: Eugeni Dodonov Signed-off-by: Keith Packard --- drivers/gpu/drm/i915/intel_display.c | 25 ------------------------- 1 file changed, 25 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 921253c..981b1f1 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5620,31 +5620,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, } } - /* enable transcoder DPLL */ - if (HAS_PCH_CPT(dev)) { - u32 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL : - TRANSC_DPLLB_SEL; - temp = I915_READ(PCH_DPLL_SEL); - switch (pipe) { - case 0: - temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL; - break; - case 1: - temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL; - break; - case 2: - temp &= ~(TRANSC_DPLLB_SEL); - temp |= TRANSC_DPLL_ENABLE | transc_sel; - break; - default: - BUG(); - } - I915_WRITE(PCH_DPLL_SEL, temp); - - POSTING_READ(PCH_DPLL_SEL); - udelay(150); - } - /* The LVDS pin pair needs to be on before the DPLLs are enabled. * This is an exception to the general rule that mode_set doesn't turn * things on. -- 2.7.4