From a42b7247d36a43d5c5b58c99aafce9ad6d1fe796 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 27 Mar 2019 16:58:22 +0000 Subject: [PATCH] AMDGPU: Fix missing scc implicit def on s_andn2_b64_term Introduce new helper class to copy properties directly from the base instruction. llvm-svn: 357089 --- llvm/lib/Target/AMDGPU/SIInstructions.td | 31 +++++++++----------- .../coalescer-subranges-another-prune-error.mir | 4 +-- .../AMDGPU/coalescer-subregjoin-fullcopy.mir | 2 +- .../AMDGPU/coalescing-with-subregs-in-loop-bug.mir | 2 +- llvm/test/CodeGen/AMDGPU/fix-wwm-liveness.mir | 34 +++++++++++----------- 5 files changed, 34 insertions(+), 39 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index c3fa1bb..bad6c3d 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -168,27 +168,22 @@ def GET_GROUPSTATICSIZE : SPseudoInstSI <(outs SReg_32:$sdst), (ins), [(set SReg_32:$sdst, (int_amdgcn_groupstaticsize))]>; } // End let usesCustomInserter = 1, SALU = 1 -def S_MOV_B64_term : SPseudoInstSI<(outs SReg_64:$dst), - (ins SSrc_b64:$src0)> { - let isAsCheapAsAMove = 1; - let isTerminator = 1; - let hasSideEffects = 0; -} - -def S_XOR_B64_term : SPseudoInstSI<(outs SReg_64:$dst), - (ins SSrc_b64:$src0, SSrc_b64:$src1)> { - let isAsCheapAsAMove = 1; +// Wrap an instruction by duplicating it, except for setting isTerminator. +class WrapTerminatorInst : SPseudoInstSI< + base_inst.OutOperandList, + base_inst.InOperandList> { + let Uses = base_inst.Uses; + let Defs = base_inst.Defs; let isTerminator = 1; - let hasSideEffects = 0; - let Defs = [SCC]; + let isAsCheapAsAMove = base_inst.isAsCheapAsAMove; + let hasSideEffects = base_inst.hasSideEffects; + let UseNamedOperandTable = base_inst.UseNamedOperandTable; + let CodeSize = base_inst.CodeSize; } -def S_ANDN2_B64_term : SPseudoInstSI<(outs SReg_64:$dst), - (ins SSrc_b64:$src0, SSrc_b64:$src1)> { - let isAsCheapAsAMove = 1; - let isTerminator = 1; - let hasSideEffects = 0; -} +def S_MOV_B64_term : WrapTerminatorInst; +def S_XOR_B64_term : WrapTerminatorInst; +def S_ANDN2_B64_term : WrapTerminatorInst; def WAVE_BARRIER : SPseudoInstSI<(outs), (ins), [(int_amdgcn_wave_barrier)]> { diff --git a/llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir b/llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir index bb4fdc9..d20382c 100644 --- a/llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir +++ b/llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir @@ -159,7 +159,7 @@ body: | %17:vreg_128 = COPY killed %80 %18:vgpr_32 = COPY killed %76 %19:vreg_128 = COPY killed %77 - $exec = S_ANDN2_B64_term $exec, %60 + $exec = S_ANDN2_B64_term $exec, %60, implicit-def $scc S_CBRANCH_EXECNZ %bb.4, implicit $exec S_BRANCH %bb.6 @@ -180,7 +180,7 @@ body: | %73:sreg_64 = COPY %85 %74:vreg_128 = COPY %59 %75:vreg_128 = COPY killed %86 - $exec = S_ANDN2_B64_term $exec, %85 + $exec = S_ANDN2_B64_term $exec, %85, implicit-def $scc S_CBRANCH_EXECNZ %bb.10, implicit $exec S_BRANCH %bb.12 diff --git a/llvm/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir b/llvm/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir index 24e99d1..45585e3 100644 --- a/llvm/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir +++ b/llvm/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir @@ -95,7 +95,7 @@ body: | %28:sreg_64 = S_OR_B64 %24, killed %27, implicit-def dead $scc %5:sreg_64 = COPY %28 %6:vreg_128 = COPY killed %25 - $exec = S_ANDN2_B64_term $exec, %28 + $exec = S_ANDN2_B64_term $exec, %28, implicit-def $scc S_CBRANCH_EXECNZ %bb.6, implicit $exec S_BRANCH %bb.8 diff --git a/llvm/test/CodeGen/AMDGPU/coalescing-with-subregs-in-loop-bug.mir b/llvm/test/CodeGen/AMDGPU/coalescing-with-subregs-in-loop-bug.mir index 37a0eb4..cd4a851 100644 --- a/llvm/test/CodeGen/AMDGPU/coalescing-with-subregs-in-loop-bug.mir +++ b/llvm/test/CodeGen/AMDGPU/coalescing-with-subregs-in-loop-bug.mir @@ -83,7 +83,7 @@ body: | %43:sreg_64 = COPY %1 %44:vreg_128 = COPY %35 %45:vreg_128 = COPY killed %30 - $exec = S_ANDN2_B64_term $exec, %1 + $exec = S_ANDN2_B64_term $exec, %1, implicit-def $scc S_CBRANCH_EXECNZ %bb.1, implicit $exec S_BRANCH %bb.2 diff --git a/llvm/test/CodeGen/AMDGPU/fix-wwm-liveness.mir b/llvm/test/CodeGen/AMDGPU/fix-wwm-liveness.mir index 8049d78..dcddeb7 100644 --- a/llvm/test/CodeGen/AMDGPU/fix-wwm-liveness.mir +++ b/llvm/test/CodeGen/AMDGPU/fix-wwm-liveness.mir @@ -12,7 +12,7 @@ legalized: false regBankSelected: false selected: false tracksRegLiveness: true -registers: +registers: - { id: 0, class: sreg_64, preferred-register: '' } - { id: 1, class: sgpr_32, preferred-register: '' } - { id: 2, class: sgpr_32, preferred-register: '' } @@ -37,11 +37,11 @@ registers: - { id: 21, class: vgpr_32, preferred-register: '' } - { id: 22, class: sreg_64, preferred-register: '' } - { id: 23, class: sreg_64, preferred-register: '' } -liveins: +liveins: body: | bb.0: successors: %bb.1(0x40000000), %bb.2(0x40000000) - + %21 = V_MOV_B32_e32 0, implicit $exec %5 = V_MBCNT_LO_U32_B32_e64 -1, 0, implicit $exec %6 = V_MBCNT_HI_U32_B32_e32 -1, killed %5, implicit $exec @@ -52,10 +52,10 @@ body: | $exec = S_MOV_B64_term killed %23 SI_MASK_BRANCH %bb.2, implicit $exec S_BRANCH %bb.1 - + bb.1: successors: %bb.2(0x80000000) - + %13 = S_MOV_B32 61440 %14 = S_MOV_B32 -1 %15 = REG_SEQUENCE undef %12, 1, undef %10, 2, killed %14, 3, killed %13, 4 @@ -67,7 +67,7 @@ body: | %21 = V_MOV_B32_e32 1, implicit $exec early-clobber %18 = WWM killed %17, implicit $exec BUFFER_STORE_DWORD_OFFSET killed %18, killed %15, 0, 0, 0, 0, 0, implicit $exec :: (store 4) - + bb.2: $exec = S_OR_B64 $exec, killed %0, implicit-def $scc $vgpr0 = COPY killed %21 @@ -91,7 +91,7 @@ regBankSelected: false selected: false failedISel: false tracksRegLiveness: true -registers: +registers: - { id: 0, class: vgpr_32, preferred-register: '' } - { id: 1, class: sreg_32_xm0, preferred-register: '' } - { id: 2, class: sreg_64, preferred-register: '' } @@ -120,8 +120,8 @@ registers: - { id: 25, class: sreg_64, preferred-register: '' } - { id: 26, class: sreg_64, preferred-register: '' } - { id: 27, class: vgpr_32, preferred-register: '' } -liveins: -frameInfo: +liveins: +frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false hasStackMap: false @@ -139,13 +139,13 @@ frameInfo: localFrameSize: 0 savePoint: '' restorePoint: '' -fixedStack: -stack: -constants: +fixedStack: +stack: +constants: body: | bb.0: successors: %bb.1(0x80000000) - + %25:sreg_64 = S_OR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec %0:vgpr_32 = FLAT_LOAD_DWORD undef %9:vreg_64, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load 4 from `float addrspace(1)* undef`, addrspace 1) $exec = EXIT_WWM killed %25 @@ -153,10 +153,10 @@ body: | %7:sreg_64 = S_MOV_B64 0 %26:sreg_64 = COPY killed %7 %27:vgpr_32 = COPY killed %12 - + bb.1: successors: %bb.2(0x04000000), %bb.1(0x7c000000) - + %24:sreg_64 = S_OR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec %20:vgpr_32 = COPY killed %27 %2:sreg_64 = COPY killed %26 @@ -168,10 +168,10 @@ body: | %21:vgpr_32 = COPY killed %22 %26:sreg_64 = COPY %6 %27:vgpr_32 = COPY killed %21 - $exec = S_ANDN2_B64_term $exec, %6 + $exec = S_ANDN2_B64_term $exec, %6, implicit-def $scc S_CBRANCH_EXECNZ %bb.1, implicit $exec S_BRANCH %bb.2 - + bb.2: $exec = S_OR_B64 $exec, killed %6, implicit-def $scc %23:sreg_64 = S_OR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec -- 2.7.4