From a41ae2f005c9eb5e277ca9021f87f793f06d138f Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Sun, 22 Apr 2018 10:39:16 +0000 Subject: [PATCH] [X86] Fix WriteMPSAD/WritePSADBW values to allow us to remove unnecessary instrw overrides. llvm-svn: 330542 --- llvm/lib/Target/X86/X86SchedBroadwell.td | 16 +--------------- llvm/lib/Target/X86/X86SchedHaswell.td | 16 +--------------- llvm/lib/Target/X86/X86SchedSandyBridge.td | 16 +--------------- llvm/lib/Target/X86/X86SchedSkylakeClient.td | 16 +--------------- llvm/lib/Target/X86/X86SchedSkylakeServer.td | 15 ++++----------- llvm/test/CodeGen/X86/avx2-schedule.ll | 4 ++-- 6 files changed, 10 insertions(+), 73 deletions(-) diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td index 3fc7643..22ea724 100755 --- a/llvm/lib/Target/X86/X86SchedBroadwell.td +++ b/llvm/lib/Target/X86/X86SchedBroadwell.td @@ -187,7 +187,7 @@ defm : BWWriteResPair; // Vector shuffles. defm : BWWriteResPair; // Vector variable shuffles. defm : BWWriteResPair; // Vector blends. defm : BWWriteResPair; // Vector variable blends. -defm : BWWriteResPair; // Vector MPSAD. +defm : BWWriteResPair; // Vector MPSAD. defm : BWWriteResPair; // Vector PSADBW. // Conversion between integer and float. @@ -1335,13 +1335,6 @@ def: InstRW<[BWWriteResGroup77], (instregex "VBLENDPDYrmi", "VPORYrm", "VPXORYrm")>; -def BWWriteResGroup78 : SchedWriteRes<[BWPort0,BWPort5]> { - let Latency = 7; - let NumMicroOps = 3; - let ResourceCycles = [1,2]; -} -def: InstRW<[BWWriteResGroup78], (instregex "(V?)MPSADBW(Y?)rri")>; - def BWWriteResGroup79 : SchedWriteRes<[BWPort5,BWPort23]> { let Latency = 7; let NumMicroOps = 3; @@ -1923,13 +1916,6 @@ def: InstRW<[BWWriteResGroup135], (instregex "ADD_FI16m", "VROUNDPDYm", "VROUNDPSYm")>; -def BWWriteResGroup136 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> { - let Latency = 12; - let NumMicroOps = 4; - let ResourceCycles = [1,2,1]; -} -def: InstRW<[BWWriteResGroup136], (instregex "(V?)MPSADBWrmi")>; - def BWWriteResGroup137 : SchedWriteRes<[BWPort0,BWFPDivider]> { let Latency = 11; let NumMicroOps = 1; diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td index e992440..18e33a8 100644 --- a/llvm/lib/Target/X86/X86SchedHaswell.td +++ b/llvm/lib/Target/X86/X86SchedHaswell.td @@ -186,7 +186,7 @@ defm : HWWriteResPair; defm : HWWriteResPair; defm : HWWriteResPair; defm : HWWriteResPair; -defm : HWWriteResPair; +defm : HWWriteResPair; defm : HWWriteResPair; // String instructions. @@ -2227,20 +2227,6 @@ def HWWriteResGroup109 : SchedWriteRes<[HWPort1,HWPort23,HWPort237,HWPort06,HWPo def: InstRW<[HWWriteResGroup109], (instregex "SHLD(16|32|64)mrCL", "SHRD(16|32|64)mrCL")>; -def HWWriteResGroup112 : SchedWriteRes<[HWPort0,HWPort5]> { - let Latency = 7; - let NumMicroOps = 3; - let ResourceCycles = [1,2]; -} -def: InstRW<[HWWriteResGroup112], (instregex "(V?)MPSADBW(Y?)rri")>; - -def HWWriteResGroup113 : SchedWriteRes<[HWPort0,HWPort5,HWPort23]> { - let Latency = 13; - let NumMicroOps = 4; - let ResourceCycles = [1,2,1]; -} -def: InstRW<[HWWriteResGroup113], (instregex "(V?)MPSADBWrmi")>; - def HWWriteResGroup113_1 : SchedWriteRes<[HWPort0,HWPort5,HWPort23]> { let Latency = 14; let NumMicroOps = 4; diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td index 6599507..5fcfda7 100644 --- a/llvm/lib/Target/X86/X86SchedSandyBridge.td +++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td @@ -170,7 +170,7 @@ defm : SBWriteResPair; defm : SBWriteResPair; defm : SBWriteResPair; defm : SBWriteResPair; -defm : SBWriteResPair; +defm : SBWriteResPair; defm : SBWriteResPair; //////////////////////////////////////////////////////////////////////////////// @@ -789,13 +789,6 @@ def SBWriteResGroup33 : SchedWriteRes<[SBPort4,SBPort23]> { def: InstRW<[SBWriteResGroup33], (instregex "PUSH64i8", "PUSH(16|32|64)r")>; -def SBWriteResGroup34 : SchedWriteRes<[SBPort0,SBPort15]> { - let Latency = 7; - let NumMicroOps = 3; - let ResourceCycles = [1,2]; -} -def: InstRW<[SBWriteResGroup34], (instregex "(V?)MPSADBWrri")>; - def SBWriteResGroup35 : SchedWriteRes<[SBPort1,SBPort5]> { let Latency = 5; let NumMicroOps = 3; @@ -1649,13 +1642,6 @@ def: InstRW<[SBWriteResGroup107], (instregex "VCVTPD2DQYrm", "VCVTPD2PSYrm", "VCVTTPD2DQYrm")>; -def SBWriteResGroup108 : SchedWriteRes<[SBPort0,SBPort23,SBPort15]> { - let Latency = 13; - let NumMicroOps = 4; - let ResourceCycles = [1,1,2]; -} -def: InstRW<[SBWriteResGroup108], (instregex "(V?)MPSADBWrmi")>; - def SBWriteResGroup109 : SchedWriteRes<[SBPort1,SBPort5,SBPort23]> { let Latency = 11; let NumMicroOps = 4; diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td index 8f686bf..f661f34 100644 --- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td @@ -184,7 +184,7 @@ defm : SKLWriteResPair; // Vector shuffles. defm : SKLWriteResPair; // Vector shuffles. defm : SKLWriteResPair; // Vector blends. defm : SKLWriteResPair; // Vector variable blends. -defm : SKLWriteResPair; // Vector MPSAD. +defm : SKLWriteResPair; // Vector MPSAD. defm : SKLWriteResPair; // Vector PSADBW. // Conversion between integer and float. @@ -958,13 +958,6 @@ def: InstRW<[SKLWriteResGroup48], (instregex "(V?)ADDPD(Y?)rr", "(V?)SUBSDrr", "(V?)SUBSSrr")>; -def SKLWriteResGroup50 : SchedWriteRes<[SKLPort5]> { - let Latency = 4; - let NumMicroOps = 2; - let ResourceCycles = [2]; -} -def: InstRW<[SKLWriteResGroup50], (instregex "(V?)MPSADBW(Y?)rri")>; - def SKLWriteResGroup51 : SchedWriteRes<[SKLPort1,SKLPort5]> { let Latency = 4; let NumMicroOps = 2; @@ -1993,13 +1986,6 @@ def: InstRW<[SKLWriteResGroup134], (instregex "(V?)ADDPDrm", def: InstRW<[SKLWriteResGroup134], (instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)m")>; -def SKLWriteResGroup137 : SchedWriteRes<[SKLPort5,SKLPort23]> { - let Latency = 10; - let NumMicroOps = 3; - let ResourceCycles = [2,1]; -} -def: InstRW<[SKLWriteResGroup137], (instregex "(V?)MPSADBWrmi")>; - def SKLWriteResGroup138 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { let Latency = 10; let NumMicroOps = 3; diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td index 10f7dc2..7268358 100755 --- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td @@ -184,8 +184,8 @@ defm : SKXWriteResPair; // Vector shuffles. defm : SKXWriteResPair; // Vector variable shuffles. defm : SKXWriteResPair; // Vector blends. defm : SKXWriteResPair; // Vector variable blends. -defm : SKXWriteResPair; // Vector MPSAD. -defm : SKXWriteResPair; // Vector PSADBW. +defm : SKXWriteResPair; // Vector MPSAD. +defm : SKXWriteResPair; // Vector PSADBW. // Conversion between integer and float. defm : SKXWriteResPair; // Float -> Integer. @@ -1869,15 +1869,12 @@ def SKXWriteResGroup51 : SchedWriteRes<[SKXPort5]> { let NumMicroOps = 2; let ResourceCycles = [2]; } -def: InstRW<[SKXWriteResGroup51], (instregex "MPSADBWrri", - "VEXPANDPDZ128rr", +def: InstRW<[SKXWriteResGroup51], (instregex "VEXPANDPDZ128rr", "VEXPANDPDZ256rr", "VEXPANDPDZrr", "VEXPANDPSZ128rr", "VEXPANDPSZ256rr", "VEXPANDPSZrr", - "VMPSADBWYrri", - "VMPSADBWrri", "VPEXPANDDZ128rr", "VPEXPANDDZ256rr", "VPEXPANDDZrr", @@ -3702,7 +3699,6 @@ def SKXWriteResGroup136 : SchedWriteRes<[SKXPort5,SKXPort23]> { let ResourceCycles = [1,1]; } def: InstRW<[SKXWriteResGroup136], (instregex "PCMPGTQrm", - "PSADBWrm", "VALIGNDZ128rm(b?)i", "VALIGNQZ128rm(b?)i", "VCMPPDZ128rm(b?)i", @@ -3757,7 +3753,6 @@ def: InstRW<[SKXWriteResGroup136], (instregex "PCMPGTQrm", "VPMOVZXWDZ128rm(b?)", "VPMOVZXWQZ128rm(b?)", "VPSADBWZ128rm(b?)", - "VPSADBWrm", "VPTESTMBZ128rm(b?)", "VPTESTMDZ128rm(b?)", "VPTESTMQZ128rm(b?)", @@ -4179,10 +4174,8 @@ def SKXWriteResGroup151 : SchedWriteRes<[SKXPort5,SKXPort23]> { let NumMicroOps = 3; let ResourceCycles = [2,1]; } -def: InstRW<[SKXWriteResGroup151], (instregex "MPSADBWrmi", - "VEXPANDPDZ128rm(b?)", +def: InstRW<[SKXWriteResGroup151], (instregex "VEXPANDPDZ128rm(b?)", "VEXPANDPSZ128rm(b?)", - "VMPSADBWrmi", "VPEXPANDDZ128rm(b?)", "VPEXPANDQZ128rm(b?)")>; diff --git a/llvm/test/CodeGen/X86/avx2-schedule.ll b/llvm/test/CodeGen/X86/avx2-schedule.ll index f7e8ccf..6adfed7 100644 --- a/llvm/test/CodeGen/X86/avx2-schedule.ll +++ b/llvm/test/CodeGen/X86/avx2-schedule.ll @@ -608,8 +608,8 @@ declare <4 x i64> @llvm.x86.avx2.movntdqa(i8*) nounwind readonly define <16 x i16> @test_mpsadbw(<32 x i8> %a0, <32 x i8> %a1, <32 x i8> *%a2) { ; GENERIC-LABEL: test_mpsadbw: ; GENERIC: # %bb.0: -; GENERIC-NEXT: vmpsadbw $7, %ymm1, %ymm0, %ymm0 # sched: [5:1.00] -; GENERIC-NEXT: vmpsadbw $7, (%rdi), %ymm0, %ymm0 # sched: [10:1.00] +; GENERIC-NEXT: vmpsadbw $7, %ymm1, %ymm0, %ymm0 # sched: [7:1.00] +; GENERIC-NEXT: vmpsadbw $7, (%rdi), %ymm0, %ymm0 # sched: [13:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00] ; ; HASWELL-LABEL: test_mpsadbw: -- 2.7.4