From a403ad4f5a034e52a3cd845e91c4aa3e6927b731 Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Wed, 25 Nov 2015 15:15:20 +0200 Subject: [PATCH] i965: Add slice count to the brw_device_info structure. MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Reviewed-by: Samuel Iglesias Gonsálvez Reviewed-by: Kristian Høgsberg --- src/mesa/drivers/dri/i965/brw_device_info.c | 20 ++++++++++++++++++++ src/mesa/drivers/dri/i965/brw_device_info.h | 5 +++++ 2 files changed, 25 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c b/src/mesa/drivers/dri/i965/brw_device_info.c index f4a9356..4bfc831 100644 --- a/src/mesa/drivers/dri/i965/brw_device_info.c +++ b/src/mesa/drivers/dri/i965/brw_device_info.c @@ -28,6 +28,7 @@ static const struct brw_device_info brw_device_info_i965 = { .gen = 4, .has_negative_rhw_bug = true, + .num_slices = 1, .max_vs_threads = 16, .max_gs_threads = 2, .max_wm_threads = 8 * 4, @@ -42,6 +43,7 @@ static const struct brw_device_info brw_device_info_g4x = { .has_compr4 = true, .has_surface_tile_offset = true, .is_g4x = true, + .num_slices = 1, .max_vs_threads = 32, .max_gs_threads = 2, .max_wm_threads = 10 * 5, @@ -55,6 +57,7 @@ static const struct brw_device_info brw_device_info_ilk = { .has_pln = true, .has_compr4 = true, .has_surface_tile_offset = true, + .num_slices = 1, .max_vs_threads = 72, .max_gs_threads = 32, .max_wm_threads = 12 * 6, @@ -71,6 +74,7 @@ static const struct brw_device_info brw_device_info_snb_gt1 = { .has_pln = true, .has_surface_tile_offset = true, .needs_unlit_centroid_workaround = true, + .num_slices = 1, .max_vs_threads = 24, .max_gs_threads = 21, /* conservative; 24 if rendering disabled. */ .max_wm_threads = 40, @@ -90,6 +94,7 @@ static const struct brw_device_info brw_device_info_snb_gt2 = { .has_pln = true, .has_surface_tile_offset = true, .needs_unlit_centroid_workaround = true, + .num_slices = 1, .max_vs_threads = 60, .max_gs_threads = 60, .max_wm_threads = 80, @@ -112,6 +117,7 @@ static const struct brw_device_info brw_device_info_snb_gt2 = { static const struct brw_device_info brw_device_info_ivb_gt1 = { GEN7_FEATURES, .is_ivybridge = true, .gt = 1, .needs_unlit_centroid_workaround = true, + .num_slices = 1, .max_vs_threads = 36, .max_hs_threads = 36, .max_ds_threads = 36, @@ -132,6 +138,7 @@ static const struct brw_device_info brw_device_info_ivb_gt1 = { static const struct brw_device_info brw_device_info_ivb_gt2 = { GEN7_FEATURES, .is_ivybridge = true, .gt = 2, .needs_unlit_centroid_workaround = true, + .num_slices = 1, .max_vs_threads = 128, .max_hs_threads = 128, .max_ds_threads = 128, @@ -152,6 +159,7 @@ static const struct brw_device_info brw_device_info_ivb_gt2 = { static const struct brw_device_info brw_device_info_byt = { GEN7_FEATURES, .is_baytrail = true, .gt = 1, .needs_unlit_centroid_workaround = true, + .num_slices = 1, .has_llc = false, .max_vs_threads = 36, .max_hs_threads = 36, @@ -178,6 +186,7 @@ static const struct brw_device_info brw_device_info_byt = { static const struct brw_device_info brw_device_info_hsw_gt1 = { HSW_FEATURES, .gt = 1, + .num_slices = 1, .max_vs_threads = 70, .max_hs_threads = 70, .max_ds_threads = 70, @@ -197,6 +206,7 @@ static const struct brw_device_info brw_device_info_hsw_gt1 = { static const struct brw_device_info brw_device_info_hsw_gt2 = { HSW_FEATURES, .gt = 2, + .num_slices = 1, .max_vs_threads = 280, .max_hs_threads = 256, .max_ds_threads = 280, @@ -216,6 +226,7 @@ static const struct brw_device_info brw_device_info_hsw_gt2 = { static const struct brw_device_info brw_device_info_hsw_gt3 = { HSW_FEATURES, .gt = 3, + .num_slices = 2, .max_vs_threads = 280, .max_hs_threads = 256, .max_ds_threads = 280, @@ -249,6 +260,7 @@ static const struct brw_device_info brw_device_info_hsw_gt3 = { static const struct brw_device_info brw_device_info_bdw_gt1 = { GEN8_FEATURES, .gt = 1, + .num_slices = 1, .max_cs_threads = 42, .urb = { .size = 192, @@ -263,6 +275,7 @@ static const struct brw_device_info brw_device_info_bdw_gt1 = { static const struct brw_device_info brw_device_info_bdw_gt2 = { GEN8_FEATURES, .gt = 2, + .num_slices = 1, .max_cs_threads = 56, .urb = { .size = 384, @@ -277,6 +290,7 @@ static const struct brw_device_info brw_device_info_bdw_gt2 = { static const struct brw_device_info brw_device_info_bdw_gt3 = { GEN8_FEATURES, .gt = 3, + .num_slices = 2, .max_cs_threads = 56, .urb = { .size = 384, @@ -292,6 +306,7 @@ static const struct brw_device_info brw_device_info_bdw_gt3 = { static const struct brw_device_info brw_device_info_chv = { GEN8_FEATURES, .is_cherryview = 1, .gt = 1, .has_llc = false, + .num_slices = 1, .max_vs_threads = 80, .max_hs_threads = 80, .max_ds_threads = 80, @@ -335,19 +350,23 @@ static const struct brw_device_info brw_device_info_chv = { static const struct brw_device_info brw_device_info_skl_gt1 = { GEN9_FEATURES, .gt = 1, + .num_slices = 1, .urb.size = 192, }; static const struct brw_device_info brw_device_info_skl_gt2 = { GEN9_FEATURES, .gt = 2, + .num_slices = 1, }; static const struct brw_device_info brw_device_info_skl_gt3 = { GEN9_FEATURES, .gt = 3, + .num_slices = 2, }; static const struct brw_device_info brw_device_info_skl_gt4 = { GEN9_FEATURES, .gt = 4, + .num_slices = 3, /* From the "L3 Allocation and Programming" documentation: * * "URB is limited to 1008KB due to programming restrictions. This is not a @@ -366,6 +385,7 @@ static const struct brw_device_info brw_device_info_bxt = { .has_llc = false, /* XXX: These are preliminary thread counts and URB sizes. */ + .num_slices = 1, .max_vs_threads = 56, .max_hs_threads = 56, .max_ds_threads = 56, diff --git a/src/mesa/drivers/dri/i965/brw_device_info.h b/src/mesa/drivers/dri/i965/brw_device_info.h index af85201..4a8fc53 100644 --- a/src/mesa/drivers/dri/i965/brw_device_info.h +++ b/src/mesa/drivers/dri/i965/brw_device_info.h @@ -68,6 +68,11 @@ struct brw_device_info * GPU Limits: * @{ */ + /** + * Total number of slices present on the device whether or not they've been + * fused off. + */ + unsigned num_slices; unsigned max_vs_threads; unsigned max_hs_threads; unsigned max_ds_threads; -- 2.7.4