From a3d1e03cd7a6e3d4ba91e3f0eca33003d679ea4a Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Fri, 9 Sep 2016 21:47:21 +0000 Subject: [PATCH] [X86][XOP] Fix VPERMIL2PD mask creation on 32-bit targets Use getConstVector helper to correctly create v2i64/v4i64 constants on 32-bit targets llvm-svn: 281105 --- llvm/lib/Target/X86/X86ISelLowering.cpp | 10 +- .../CodeGen/X86/vector-shuffle-combining-xop.ll | 223 ++++++++++++++------- 2 files changed, 160 insertions(+), 73 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 6236685..987447d 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -25469,29 +25469,29 @@ static bool combineX86ShuffleChain(ArrayRef Inputs, SDValue Root, // Bits[2:0] - (Per Lane) PS Shuffle Mask. unsigned NumLanes = MaskVT.getSizeInBits() / 128; unsigned NumEltsPerLane = NumMaskElts / NumLanes; - SmallVector VPerm2Idx; + SmallVector VPerm2Idx; MVT MaskIdxSVT = MVT::getIntegerVT(MaskVT.getScalarSizeInBits()); MVT MaskIdxVT = MVT::getVectorVT(MaskIdxSVT, NumMaskElts); unsigned M2ZImm = 0; for (int M : Mask) { if (M == SM_SentinelUndef) { - VPerm2Idx.push_back(DAG.getUNDEF(MaskIdxSVT)); + VPerm2Idx.push_back(-1); continue; } if (M == SM_SentinelZero) { M2ZImm = 2; - VPerm2Idx.push_back(DAG.getConstant(8, DL, MaskIdxSVT)); + VPerm2Idx.push_back(8); continue; } int Index = (M % NumEltsPerLane) + ((M / NumMaskElts) * NumEltsPerLane); Index = (MaskVT.getScalarSizeInBits() == 64 ? Index << 1 : Index); - VPerm2Idx.push_back(DAG.getConstant(Index, DL, MaskIdxSVT)); + VPerm2Idx.push_back(Index); } V1 = DAG.getBitcast(MaskVT, V1); DCI.AddToWorklist(V1.getNode()); V2 = DAG.getBitcast(MaskVT, V2); DCI.AddToWorklist(V2.getNode()); - SDValue VPerm2MaskOp = DAG.getBuildVector(MaskIdxVT, DL, VPerm2Idx); + SDValue VPerm2MaskOp = getConstVector(VPerm2Idx, MaskIdxVT, DAG, DL, true); DCI.AddToWorklist(VPerm2MaskOp.getNode()); Res = DAG.getNode(X86ISD::VPERMIL2, DL, MaskVT, V1, V2, VPerm2MaskOp, DAG.getConstant(M2ZImm, DL, MVT::i8)); diff --git a/llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll b/llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll index 9ef9da3..ae6df60 100644 --- a/llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll +++ b/llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll @@ -1,6 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+xop | FileCheck %s -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+xop | FileCheck %s +; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx,+xop | FileCheck %s --check-prefix=X32 +; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx2,+xop | FileCheck %s --check-prefix=X32 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+xop | FileCheck %s --check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+xop | FileCheck %s --check-prefix=X64 declare <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double>, <2 x double>, <2 x i64>, i8) nounwind readnone declare <4 x double> @llvm.x86.xop.vpermil2pd.256(<4 x double>, <4 x double>, <4 x i64>, i8) nounwind readnone @@ -11,109 +13,168 @@ declare <8 x float> @llvm.x86.xop.vpermil2ps.256(<8 x float>, <8 x float>, <8 x declare <16 x i8> @llvm.x86.xop.vpperm(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone define <2 x double> @combine_vpermil2pd_identity(<2 x double> %a0, <2 x double> %a1) { -; CHECK-LABEL: combine_vpermil2pd_identity: -; CHECK: # BB#0: -; CHECK-NEXT: vmovaps %xmm1, %xmm0 -; CHECK-NEXT: retq +; X32-LABEL: combine_vpermil2pd_identity: +; X32: # BB#0: +; X32-NEXT: movl $2, %eax +; X32-NEXT: vmovd %eax, %xmm2 +; X32-NEXT: vpermil2pd $0, %xmm2, %xmm0, %xmm1, %xmm0 +; X32-NEXT: vpermil2pd $0, %xmm2, %xmm0, %xmm0, %xmm0 +; X32-NEXT: retl +; +; X64-LABEL: combine_vpermil2pd_identity: +; X64: # BB#0: +; X64-NEXT: vmovaps %xmm1, %xmm0 +; X64-NEXT: retq %res0 = call <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double> %a1, <2 x double> %a0, <2 x i64> , i8 0) %res1 = call <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double> %res0, <2 x double> undef, <2 x i64> , i8 0) ret <2 x double> %res1 } define <4 x double> @combine_vpermil2pd256_identity(<4 x double> %a0, <4 x double> %a1) { -; CHECK-LABEL: combine_vpermil2pd256_identity: -; CHECK: # BB#0: -; CHECK-NEXT: vmovaps %ymm1, %ymm0 -; CHECK-NEXT: retq +; X32-LABEL: combine_vpermil2pd256_identity: +; X32: # BB#0: +; X32-NEXT: vmovaps %ymm1, %ymm0 +; X32-NEXT: retl +; +; X64-LABEL: combine_vpermil2pd256_identity: +; X64: # BB#0: +; X64-NEXT: vmovaps %ymm1, %ymm0 +; X64-NEXT: retq %res0 = call <4 x double> @llvm.x86.xop.vpermil2pd.256(<4 x double> %a1, <4 x double> %a0, <4 x i64> , i8 0) %res1 = call <4 x double> @llvm.x86.xop.vpermil2pd.256(<4 x double> %res0, <4 x double> undef, <4 x i64> , i8 0) ret <4 x double> %res1 } define <4 x double> @combine_vpermil2pd256_0z73(<4 x double> %a0, <4 x double> %a1) { -; CHECK-LABEL: combine_vpermil2pd256_0z73: -; CHECK: # BB#0: -; CHECK-NEXT: vpermil2pd {{.*#+}} ymm0 = ymm0[0],zero,ymm1[3],ymm0[3] -; CHECK-NEXT: retq +; X32-LABEL: combine_vpermil2pd256_0z73: +; X32: # BB#0: +; X32-NEXT: vpermil2pd {{.*#+}} ymm0 = ymm0[0],zero,ymm1[3],ymm0[3] +; X32-NEXT: retl +; +; X64-LABEL: combine_vpermil2pd256_0z73: +; X64: # BB#0: +; X64-NEXT: vpermil2pd {{.*#+}} ymm0 = ymm0[0],zero,ymm1[3],ymm0[3] +; X64-NEXT: retq %res0 = shufflevector <4 x double> %a0, <4 x double> %a1, <4 x i32> %res1 = shufflevector <4 x double> %res0, <4 x double> zeroinitializer, <4 x i32> ret <4 x double> %res1 } define <4 x float> @combine_vpermil2ps_identity(<4 x float> %a0, <4 x float> %a1) { -; CHECK-LABEL: combine_vpermil2ps_identity: -; CHECK: # BB#0: -; CHECK-NEXT: vmovaps %xmm1, %xmm0 -; CHECK-NEXT: retq +; X32-LABEL: combine_vpermil2ps_identity: +; X32: # BB#0: +; X32-NEXT: vmovaps %xmm1, %xmm0 +; X32-NEXT: retl +; +; X64-LABEL: combine_vpermil2ps_identity: +; X64: # BB#0: +; X64-NEXT: vmovaps %xmm1, %xmm0 +; X64-NEXT: retq %res0 = call <4 x float> @llvm.x86.xop.vpermil2ps(<4 x float> %a1, <4 x float> %a0, <4 x i32> , i8 0) %res1 = call <4 x float> @llvm.x86.xop.vpermil2ps(<4 x float> %res0, <4 x float> undef, <4 x i32> , i8 0) ret <4 x float> %res1 } define <4 x float> @combine_vpermil2ps_1z74(<4 x float> %a0, <4 x float> %a1) { -; CHECK-LABEL: combine_vpermil2ps_1z74: -; CHECK: # BB#0: -; CHECK-NEXT: vpermil2ps {{.*#+}} xmm0 = xmm0[1],zero,xmm1[3,0] -; CHECK-NEXT: retq +; X32-LABEL: combine_vpermil2ps_1z74: +; X32: # BB#0: +; X32-NEXT: vpermil2ps {{.*#+}} xmm0 = xmm0[1],zero,xmm1[3,0] +; X32-NEXT: retl +; +; X64-LABEL: combine_vpermil2ps_1z74: +; X64: # BB#0: +; X64-NEXT: vpermil2ps {{.*#+}} xmm0 = xmm0[1],zero,xmm1[3,0] +; X64-NEXT: retq %res0 = call <4 x float> @llvm.x86.xop.vpermil2ps(<4 x float> %a0, <4 x float> %a1, <4 x i32> , i8 0) %res1 = shufflevector <4 x float> %res0, <4 x float> zeroinitializer, <4 x i32> ret <4 x float> %res1 } define <8 x float> @combine_vpermil2ps256_identity(<8 x float> %a0, <8 x float> %a1) { -; CHECK-LABEL: combine_vpermil2ps256_identity: -; CHECK: # BB#0: -; CHECK-NEXT: vmovaps %ymm1, %ymm0 -; CHECK-NEXT: retq +; X32-LABEL: combine_vpermil2ps256_identity: +; X32: # BB#0: +; X32-NEXT: vmovaps %ymm1, %ymm0 +; X32-NEXT: retl +; +; X64-LABEL: combine_vpermil2ps256_identity: +; X64: # BB#0: +; X64-NEXT: vmovaps %ymm1, %ymm0 +; X64-NEXT: retq %res0 = call <8 x float> @llvm.x86.xop.vpermil2ps.256(<8 x float> %a1, <8 x float> %a0, <8 x i32> , i8 0) %res1 = call <8 x float> @llvm.x86.xop.vpermil2ps.256(<8 x float> %res0, <8 x float> undef, <8 x i32> , i8 0) ret <8 x float> %res1 } define <8 x float> @combine_vpermil2ps256_08z945Az(<8 x float> %a0, <8 x float> %a1) { -; CHECK-LABEL: combine_vpermil2ps256_08z945Az: -; CHECK: # BB#0: -; CHECK-NEXT: vpermil2ps {{.*#+}} ymm0 = ymm0[0],ymm1[0],zero,ymm1[1],ymm0[4,5],ymm1[6],zero -; CHECK-NEXT: retq +; X32-LABEL: combine_vpermil2ps256_08z945Az: +; X32: # BB#0: +; X32-NEXT: vpermil2ps {{.*#+}} ymm0 = ymm0[0],ymm1[0],zero,ymm1[1],ymm0[4,5],ymm1[6],zero +; X32-NEXT: retl +; +; X64-LABEL: combine_vpermil2ps256_08z945Az: +; X64: # BB#0: +; X64-NEXT: vpermil2ps {{.*#+}} ymm0 = ymm0[0],ymm1[0],zero,ymm1[1],ymm0[4,5],ymm1[6],zero +; X64-NEXT: retq %res0 = call <8 x float> @llvm.x86.xop.vpermil2ps.256(<8 x float> %a0, <8 x float> %a1, <8 x i32> , i8 0) %res1 = shufflevector <8 x float> %res0, <8 x float> zeroinitializer, <8 x i32> ret <8 x float> %res1 } define <8 x float> @combine_vpermil2ps256_zero(<8 x float> %a0, <8 x float> %a1) { -; CHECK-LABEL: combine_vpermil2ps256_zero: -; CHECK: # BB#0: -; CHECK-NEXT: vxorps %ymm0, %ymm0, %ymm0 -; CHECK-NEXT: retq +; X32-LABEL: combine_vpermil2ps256_zero: +; X32: # BB#0: +; X32-NEXT: vxorps %ymm0, %ymm0, %ymm0 +; X32-NEXT: retl +; +; X64-LABEL: combine_vpermil2ps256_zero: +; X64: # BB#0: +; X64-NEXT: vxorps %ymm0, %ymm0, %ymm0 +; X64-NEXT: retq %res0 = call <8 x float> @llvm.x86.xop.vpermil2ps.256(<8 x float> %a1, <8 x float> %a0, <8 x i32> , i8 2) ret <8 x float> %res0 } define <4 x float> @combine_vpermil2ps_blend_with_zero(<4 x float> %a0, <4 x float> %a1) { -; CHECK-LABEL: combine_vpermil2ps_blend_with_zero: -; CHECK: # BB#0: -; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1 -; CHECK-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] -; CHECK-NEXT: retq +; X32-LABEL: combine_vpermil2ps_blend_with_zero: +; X32: # BB#0: +; X32-NEXT: vxorps %xmm1, %xmm1, %xmm1 +; X32-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] +; X32-NEXT: retl +; +; X64-LABEL: combine_vpermil2ps_blend_with_zero: +; X64: # BB#0: +; X64-NEXT: vxorps %xmm1, %xmm1, %xmm1 +; X64-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] +; X64-NEXT: retq %res0 = call <4 x float> @llvm.x86.xop.vpermil2ps(<4 x float> %a0, <4 x float> %a1, <4 x i32> , i8 2) ret <4 x float> %res0 } define <16 x i8> @combine_vpperm_identity(<16 x i8> %a0, <16 x i8> %a1) { -; CHECK-LABEL: combine_vpperm_identity: -; CHECK: # BB#0: -; CHECK-NEXT: vmovaps %xmm1, %xmm0 -; CHECK-NEXT: retq +; X32-LABEL: combine_vpperm_identity: +; X32: # BB#0: +; X32-NEXT: vmovaps %xmm1, %xmm0 +; X32-NEXT: retl +; +; X64-LABEL: combine_vpperm_identity: +; X64: # BB#0: +; X64-NEXT: vmovaps %xmm1, %xmm0 +; X64-NEXT: retq %res0 = call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> ) %res1 = call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %res0, <16 x i8> undef, <16 x i8> ) ret <16 x i8> %res1 } define <16 x i8> @combine_vpperm_zero(<16 x i8> %a0, <16 x i8> %a1) { -; CHECK-LABEL: combine_vpperm_zero: -; CHECK: # BB#0: -; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0 -; CHECK-NEXT: retq +; X32-LABEL: combine_vpperm_zero: +; X32: # BB#0: +; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0 +; X32-NEXT: retl +; +; X64-LABEL: combine_vpperm_zero: +; X64: # BB#0: +; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0 +; X64-NEXT: retq %res0 = call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> ) %res1 = call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %res0, <16 x i8> undef, <16 x i8> ) %res2 = call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %res1, <16 x i8> undef, <16 x i8> ) @@ -121,10 +182,15 @@ define <16 x i8> @combine_vpperm_zero(<16 x i8> %a0, <16 x i8> %a1) { } define <16 x i8> @combine_vpperm_identity_bitcast(<16 x i8> %a0, <16 x i8> %a1) { -; CHECK-LABEL: combine_vpperm_identity_bitcast: -; CHECK: # BB#0: -; CHECK-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm0 -; CHECK-NEXT: retq +; X32-LABEL: combine_vpperm_identity_bitcast: +; X32: # BB#0: +; X32-NEXT: vpaddq {{\.LCPI.*}}, %xmm0, %xmm0 +; X32-NEXT: retl +; +; X64-LABEL: combine_vpperm_identity_bitcast: +; X64: # BB#0: +; X64-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm0 +; X64-NEXT: retq %mask = bitcast <2 x i64> to <16 x i8> %res0 = call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> %mask) %res1 = call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %res0, <16 x i8> undef, <16 x i8> %mask) @@ -135,38 +201,59 @@ define <16 x i8> @combine_vpperm_identity_bitcast(<16 x i8> %a0, <16 x i8> %a1) } define <16 x i8> @combine_vpperm_as_blend_with_zero(<16 x i8> %a0, <16 x i8> %a1) { -; CHECK-LABEL: combine_vpperm_as_blend_with_zero: -; CHECK: # BB#0: -; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1 -; CHECK-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3],xmm1[4,5,6,7] -; CHECK-NEXT: retq +; X32-LABEL: combine_vpperm_as_blend_with_zero: +; X32: # BB#0: +; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; X32-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3],xmm1[4,5,6,7] +; X32-NEXT: retl +; +; X64-LABEL: combine_vpperm_as_blend_with_zero: +; X64: # BB#0: +; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; X64-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3],xmm1[4,5,6,7] +; X64-NEXT: retq %res0 = call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> ) ret <16 x i8> %res0 } define <16 x i8> @combine_vpperm_as_unary_unpckhwd(<16 x i8> %a0, <16 x i8> %a1) { -; CHECK-LABEL: combine_vpperm_as_unary_unpckhwd: -; CHECK: # BB#0: -; CHECK-NEXT: vpunpckhbw {{.*#+}} xmm0 = xmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15] -; CHECK-NEXT: retq +; X32-LABEL: combine_vpperm_as_unary_unpckhwd: +; X32: # BB#0: +; X32-NEXT: vpunpckhbw {{.*#+}} xmm0 = xmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15] +; X32-NEXT: retl +; +; X64-LABEL: combine_vpperm_as_unary_unpckhwd: +; X64: # BB#0: +; X64-NEXT: vpunpckhbw {{.*#+}} xmm0 = xmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15] +; X64-NEXT: retq %res0 = call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %a0, <16 x i8> %a0, <16 x i8> ) ret <16 x i8> %res0 } define <16 x i8> @combine_vpperm_as_unpckhwd(<16 x i8> %a0, <16 x i8> %a1) { -; CHECK-LABEL: combine_vpperm_as_unpckhwd: -; CHECK: # BB#0: -; CHECK-NEXT: vpperm {{.*#+}} xmm0 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15] -; CHECK-NEXT: retq +; X32-LABEL: combine_vpperm_as_unpckhwd: +; X32: # BB#0: +; X32-NEXT: vpperm {{.*#+}} xmm0 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15] +; X32-NEXT: retl +; +; X64-LABEL: combine_vpperm_as_unpckhwd: +; X64: # BB#0: +; X64-NEXT: vpperm {{.*#+}} xmm0 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15] +; X64-NEXT: retq %res0 = call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> ) ret <16 x i8> %res0 } define <4 x i32> @combine_vpperm_10zz32BA(<4 x i32> %a0, <4 x i32> %a1) { -; CHECK-LABEL: combine_vpperm_10zz32BA: -; CHECK: # BB#0: -; CHECK-NEXT: vpperm {{.*#+}} xmm0 = xmm0[2,3,0,1],zero,zero,zero,zero,xmm0[6,7,4,5],xmm1[6,7,4,5] -; CHECK-NEXT: retq +; X32-LABEL: combine_vpperm_10zz32BA: +; X32: # BB#0: +; X32-NEXT: vpperm {{.*#+}} xmm0 = xmm0[2,3,0,1],zero,zero,zero,zero,xmm0[6,7,4,5],xmm1[6,7,4,5] +; X32-NEXT: retl +; +; X64-LABEL: combine_vpperm_10zz32BA: +; X64: # BB#0: +; X64-NEXT: vpperm {{.*#+}} xmm0 = xmm0[2,3,0,1],zero,zero,zero,zero,xmm0[6,7,4,5],xmm1[6,7,4,5] +; X64-NEXT: retq %res0 = shufflevector <4 x i32> %a0, <4 x i32> %a1, <4 x i32> %res1 = bitcast <4 x i32> %res0 to <16 x i8> %res2 = call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %res1, <16 x i8> undef, <16 x i8> ) -- 2.7.4