From a383d325f6c6c8d9bb52d1da221d9a144dfc475c Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Tue, 11 May 2021 15:14:04 +0100 Subject: [PATCH] [TargetRegisterInfo] Speed up getAllocatableSet. NFCI. MachineRegisterInfo caches the reserved register set that is computed by by TargetRegisterInfo::getReservedRegs, so call into MRI to get the reserved regs to avoid recomputing them. In particular this speeds up AMDGPU's SIFormMemoryClauses pass because AMDGPU has a particularly complicated reserved set that is expensive to compute. Differential Revision: https://reviews.llvm.org/D102318 --- llvm/lib/CodeGen/TargetRegisterInfo.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/llvm/lib/CodeGen/TargetRegisterInfo.cpp b/llvm/lib/CodeGen/TargetRegisterInfo.cpp index e95e089..f4bb715 100644 --- a/llvm/lib/CodeGen/TargetRegisterInfo.cpp +++ b/llvm/lib/CodeGen/TargetRegisterInfo.cpp @@ -267,8 +267,9 @@ BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF, } // Mask out the reserved registers - BitVector Reserved = getReservedRegs(MF); - Allocatable &= Reserved.flip(); + const MachineRegisterInfo &MRI = MF.getRegInfo(); + const BitVector &Reserved = MRI.getReservedRegs(); + Allocatable.reset(Reserved); return Allocatable; } -- 2.7.4