From a365719a248ce2856d30a70881d5a42bdf581115 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Sat, 27 Oct 2018 18:37:59 +0000 Subject: [PATCH] [X86][SSE] LowerVSELECT - pull out repeated getOperand(). NFCI. llvm-svn: 345458 --- llvm/lib/Target/X86/X86ISelLowering.cpp | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 6d589ee..c2ca889 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -15680,11 +15680,15 @@ static SDValue lowerVSELECTtoVectorShuffle(SDValue Op, } SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const { + SDValue Cond = Op.getOperand(0); + SDValue LHS = Op.getOperand(1); + SDValue RHS = Op.getOperand(2); + // A vselect where all conditions and data are constants can be optimized into // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR(). - if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) && - ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) && - ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode())) + if (ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()) && + ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) && + ISD::isBuildVectorOfConstantSDNodes(RHS.getNode())) return SDValue(); // Try to lower this to a blend-style vector shuffle. This can handle all @@ -15694,7 +15698,7 @@ SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const { // If this VSELECT has a vector if i1 as a mask, it will be directly matched // with patterns on the mask registers on AVX-512. - if (Op->getOperand(0).getValueType().getScalarSizeInBits() == 1) + if (Cond.getScalarValueSizeInBits() == 1) return Op; // Variable blends are only legal from SSE4.1 onward. @@ -15708,11 +15712,9 @@ SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const { // into an i1 condition so that we can use the mask-based 512-bit blend // instructions. if (VT.getSizeInBits() == 512) { - SDValue Cond = Op.getOperand(0); // The vNi1 condition case should be handled above as it can be trivially // lowered. - assert(Cond.getValueType().getScalarSizeInBits() == - VT.getScalarSizeInBits() && + assert(Cond.getScalarValueSizeInBits() == VT.getScalarSizeInBits() && "Should have a size-matched integer condition!"); // Build a mask by testing the condition against zero. MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements()); @@ -15720,7 +15722,7 @@ SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const { getZeroVector(VT, Subtarget, DAG, dl), ISD::SETNE); // Now return a new VSELECT using the mask. - return DAG.getSelect(dl, VT, Mask, Op.getOperand(1), Op.getOperand(2)); + return DAG.getSelect(dl, VT, Mask, LHS, RHS); } // Only some types will be legal on some subtargets. If we can emit a legal @@ -15742,9 +15744,9 @@ SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const { case MVT::v16i16: { // Bitcast everything to the vXi8 type and use a vXi8 vselect. MVT CastVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2); - SDValue Cond = DAG.getBitcast(CastVT, Op->getOperand(0)); - SDValue LHS = DAG.getBitcast(CastVT, Op->getOperand(1)); - SDValue RHS = DAG.getBitcast(CastVT, Op->getOperand(2)); + Cond = DAG.getBitcast(CastVT, Cond); + LHS = DAG.getBitcast(CastVT, LHS); + RHS = DAG.getBitcast(CastVT, RHS); SDValue Select = DAG.getNode(ISD::VSELECT, dl, CastVT, Cond, LHS, RHS); return DAG.getBitcast(VT, Select); } -- 2.7.4