From a2b2012eab25aad00a7dd587d1754115491e59eb Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Wed, 20 Mar 2019 13:13:59 -0700 Subject: [PATCH] ARM: dts: rockchip: Fix gic/efuse sort ordering for rk3288 It can be seen that 0xffb40000 < 0xffc01000, thus efuse comes first. Signed-off-by: Douglas Anderson Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288.dtsi | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index b577f3e..743a7d8 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -1379,19 +1379,6 @@ reg = <0x0 0xffaf0080 0x0 0x20>; }; - gic: interrupt-controller@ffc01000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - - reg = <0x0 0xffc01000 0x0 0x1000>, - <0x0 0xffc02000 0x0 0x2000>, - <0x0 0xffc04000 0x0 0x2000>, - <0x0 0xffc06000 0x0 0x2000>; - interrupts = ; - }; - efuse: efuse@ffb40000 { compatible = "rockchip,rk3288-efuse"; reg = <0x0 0xffb40000 0x0 0x20>; @@ -1405,6 +1392,19 @@ }; }; + gic: interrupt-controller@ffc01000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + + reg = <0x0 0xffc01000 0x0 0x1000>, + <0x0 0xffc02000 0x0 0x2000>, + <0x0 0xffc04000 0x0 0x2000>, + <0x0 0xffc06000 0x0 0x2000>; + interrupts = ; + }; + pinctrl: pinctrl { compatible = "rockchip,rk3288-pinctrl"; rockchip,grf = <&grf>; -- 2.7.4