From a2453c6130859e78d7fe9c1012c7695a8db6bcc8 Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Mon, 17 Jul 2023 12:55:27 +0100 Subject: [PATCH] [AMDGPU] Add test case for zext of f16 to i32 Preserve the test case from this abandoned review: D51925 [AMDGPU] Fix issue for zext of f16 to i32 --- llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll | 50 ++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll b/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll index 5fd6b7ca0324..00ea05b0dd24 100644 --- a/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll +++ b/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll @@ -2202,6 +2202,56 @@ define <4 x half> @v_mad_mix_v4f32_clamp_precvt(<4 x half> %src0, <4 x half> %sr ret <4 x half> %cvt.result } +define i32 @mixlo_zext(float %src0, float %src1, float %src2) #0 { +; GFX1100-LABEL: mixlo_zext: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 +; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1100-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: mixlo_zext: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_mad_mixlo_f16 v0, v0, v1, v2 +; GFX900-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: mixlo_zext: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 +; GFX906-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: mixlo_zext: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mac_f32_e32 v2, v0, v1 +; VI-NEXT: v_cvt_f16_f32_e32 v0, v2 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-CI-LABEL: mixlo_zext: +; SDAG-CI: ; %bb.0: +; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-CI-NEXT: v_mac_f32_e32 v2, v0, v1 +; SDAG-CI-NEXT: v_cvt_f16_f32_e32 v0, v2 +; SDAG-CI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-CI-LABEL: mixlo_zext: +; GISEL-CI: ; %bb.0: +; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-CI-NEXT: v_mac_f32_e32 v2, v0, v1 +; GISEL-CI-NEXT: v_cvt_f16_f32_e32 v0, v2 +; GISEL-CI-NEXT: s_setpc_b64 s[30:31] + %result = call float @llvm.fmuladd.f32(float %src0, float %src1, float %src2) + %cvt.result = fptrunc float %result to half + %cvt.result.i16 = bitcast half %cvt.result to i16 + %cvt.result.i32 = zext i16 %cvt.result.i16 to i32 + ret i32 %cvt.result.i32 +} + define half @mixlo_fptrunc(float %a, float %b) #0 { ; GFX1100-LABEL: mixlo_fptrunc: ; GFX1100: ; %bb.0: ; %.entry -- 2.34.1