From a23b13edc8a96ccf9a1c6a6bb83f1ebf3353ce5e Mon Sep 17 00:00:00 2001 From: Evoke Zhang Date: Fri, 31 Aug 2018 10:33:46 +0800 Subject: [PATCH] lcd: g12b: update hpll & gp0_pll wait lock sequence [2/2] PD#172762: lcd: g12b: update hpll & gp0_pll wait lock sequence Change-Id: If085975292682ed5570e2fc326c895d38e896449 Signed-off-by: Evoke Zhang --- drivers/amlogic/media/vout/lcd/lcd_clk_config.c | 96 ++++++++++++++++++++++++- 1 file changed, 95 insertions(+), 1 deletion(-) diff --git a/drivers/amlogic/media/vout/lcd/lcd_clk_config.c b/drivers/amlogic/media/vout/lcd/lcd_clk_config.c index eccb4cf9..91e80e2 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_clk_config.c +++ b/drivers/amlogic/media/vout/lcd/lcd_clk_config.c @@ -1047,6 +1047,91 @@ static void lcd_update_hpll_frac_g12a(struct lcd_clk_config_s *cConf) lcd_hiu_setb(HHI_HDMI_PLL_CNTL2, cConf->pll_frac, 0, 19); } +static void lcd_set_gp0_pll_g12b(struct lcd_clk_config_s *cConf) +{ + unsigned int pll_ctrl, pll_ctrl1, pll_ctrl3, pll_ctrl4, pll_ctrl6; + int ret; + + if (lcd_debug_print_flag == 2) + LCDPR("%s\n", __func__); + + pll_ctrl = ((1 << LCD_PLL_EN_GP0_G12A) | + (cConf->pll_n << LCD_PLL_N_GP0_G12A) | + (cConf->pll_m << LCD_PLL_M_GP0_G12A) | + (cConf->pll_od1_sel << LCD_PLL_OD_GP0_G12A)); + pll_ctrl1 = (cConf->pll_frac << 0); + if (cConf->pll_frac) { + pll_ctrl |= (1 << 27); + pll_ctrl3 = 0x6a285c00; + pll_ctrl4 = 0x65771290; + pll_ctrl6 = 0x56540000; + } else { + pll_ctrl3 = 0x48681c00; + pll_ctrl4 = 0x33771290; + pll_ctrl6 = 0x56540000; + } + + lcd_hiu_write(HHI_GP0_PLL_CNTL0_G12A, pll_ctrl); + lcd_hiu_write(HHI_GP0_PLL_CNTL1_G12A, pll_ctrl1); + lcd_hiu_write(HHI_GP0_PLL_CNTL2_G12A, 0x00); + lcd_hiu_write(HHI_GP0_PLL_CNTL3_G12A, pll_ctrl3); + lcd_hiu_write(HHI_GP0_PLL_CNTL4_G12A, pll_ctrl4); + lcd_hiu_write(HHI_GP0_PLL_CNTL5_G12A, 0x39272000); + lcd_hiu_write(HHI_GP0_PLL_CNTL6_G12A, pll_ctrl6); + lcd_hiu_setb(HHI_GP0_PLL_CNTL0_G12A, 1, LCD_PLL_RST_GP0_G12A, 1); + udelay(100); + lcd_hiu_setb(HHI_GP0_PLL_CNTL0_G12A, 0, LCD_PLL_RST_GP0_G12A, 1); + + ret = lcd_pll_wait_lock(HHI_GP0_PLL_CNTL0_G12A, LCD_PLL_LOCK_GP0_G12A); + if (ret) + LCDERR("gp0_pll lock failed\n"); + +} + +static void lcd_set_hpll_g12b(struct lcd_clk_config_s *cConf) +{ + unsigned int pll_ctrl, pll_ctrl2, pll_ctrl4, pll_ctrl5, pll_ctrl7; + int ret; + + if (lcd_debug_print_flag == 2) + LCDPR("%s\n", __func__); + + pll_ctrl = ((1 << LCD_PLL_EN_HPLL_G12A) | + (1 << 25) | /* clk out gate */ + (cConf->pll_n << LCD_PLL_N_HPLL_G12A) | + (cConf->pll_m << LCD_PLL_M_HPLL_G12A) | + (cConf->pll_od1_sel << LCD_PLL_OD1_HPLL_G12A) | + (cConf->pll_od2_sel << LCD_PLL_OD2_HPLL_G12A) | + (cConf->pll_od3_sel << LCD_PLL_OD3_HPLL_G12A)); + pll_ctrl2 = (cConf->pll_frac << 0); + if (cConf->pll_frac) { + pll_ctrl |= (1 << 27); + pll_ctrl4 = 0x6a285c00; + pll_ctrl5 = 0x65771290; + pll_ctrl7 = 0x56540000; + } else { + pll_ctrl4 = 0x48681c00; + pll_ctrl5 = 0x33771290; + pll_ctrl7 = 0x56540000; + } + + lcd_hiu_write(HHI_HDMI_PLL_CNTL, pll_ctrl); + lcd_hiu_write(HHI_HDMI_PLL_CNTL2, pll_ctrl2); + lcd_hiu_write(HHI_HDMI_PLL_CNTL3, 0x00); + lcd_hiu_write(HHI_HDMI_PLL_CNTL4, pll_ctrl4); + lcd_hiu_write(HHI_HDMI_PLL_CNTL5, pll_ctrl5); + lcd_hiu_write(HHI_HDMI_PLL_CNTL6, 0x39272000); + lcd_hiu_write(HHI_HDMI_PLL_CNTL7, pll_ctrl7); + lcd_hiu_setb(HHI_HDMI_PLL_CNTL, 1, LCD_PLL_RST_HPLL_G12A, 1); + udelay(100); + lcd_hiu_setb(HHI_HDMI_PLL_CNTL, 0, LCD_PLL_RST_HPLL_G12A, 1); + + ret = lcd_pll_wait_lock(HHI_HDMI_PLL_CNTL, LCD_PLL_LOCK_HPLL_G12A); + if (ret) + LCDERR("hpll lock failed\n"); + +} + static unsigned int lcd_clk_div_g9_gxtvbb[][3] = { /* divider, shift_val, shift_sel */ {CLK_DIV_SEL_1, 0xffff, 0,}, @@ -2324,7 +2409,6 @@ void lcd_clk_set(struct lcd_config_s *pconf) lcd_set_pll_axg(&clk_conf); break; case LCD_CHIP_G12A: - case LCD_CHIP_G12B: if (lcd_drv->lcd_clk_path) { /* gp0_pll */ lcd_set_gp0_pll_g12a(&clk_conf); lcd_set_dsi_phy_clk(1); @@ -2334,6 +2418,16 @@ void lcd_clk_set(struct lcd_config_s *pconf) lcd_set_dsi_phy_clk(0); } break; + case LCD_CHIP_G12B: + if (lcd_drv->lcd_clk_path) { /* gp0_pll */ + lcd_set_gp0_pll_g12b(&clk_conf); + lcd_set_dsi_phy_clk(1); + } else { /* hpll */ + lcd_set_hpll_g12b(&clk_conf); + lcd_set_vid_pll_div(&clk_conf); + lcd_set_dsi_phy_clk(0); + } + break; default: break; } -- 2.7.4