From a204eac75991691d9d55455db2b718fbfa03d81e Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Fri, 2 Oct 2020 15:49:55 -0400 Subject: [PATCH] pan/bi: Handle vector moves And fix the bad assertion that let this slip. Like combines, nir_op_vec can be vector, and we need to lower this ourselves. Thankfully, the lowering is simple. Fixes dEQP-GLES2.functional.shaders.loops.for_uniform_iterations.nested_tricky_dataflow_1_* Fixes: b2c6cf2b6db ("pan/bi: Eliminate writemasks in the IR") Signed-off-by: Alyssa Rosenzweig Reviewed-by: Boris Brezillon Part-of: --- src/panfrost/bifrost/bifrost_compile.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/src/panfrost/bifrost/bifrost_compile.c b/src/panfrost/bifrost/bifrost_compile.c index 25a6bb6..aaf3d7b 100644 --- a/src/panfrost/bifrost/bifrost_compile.c +++ b/src/panfrost/bifrost/bifrost_compile.c @@ -763,9 +763,8 @@ emit_alu(bi_context *ctx, nir_alu_instr *instr) assert((alu.type != BI_SPECIAL) || !(ctx->quirks & BIFROST_NO_FAST_OP)); unsigned comps = nir_dest_num_components(instr->dest.dest); - - if (alu.type != BI_COMBINE) - assert(comps <= MAX2(1, 32 / comps)); + bool vector = comps > MAX2(1, 32 / nir_dest_bit_size(instr->dest.dest)); + assert(!vector || alu.type == BI_COMBINE || alu.type == BI_MOV); if (!instr->dest.dest.is_ssa) { for (unsigned i = 0; i < comps; ++i) @@ -926,6 +925,15 @@ emit_alu(bi_context *ctx, nir_alu_instr *instr) break; } + if (alu.type == BI_MOV && vector) { + alu.type = BI_COMBINE; + + for (unsigned i = 0; i < comps; ++i) { + alu.src[i] = alu.src[0]; + alu.swizzle[i][0] = instr->src[0].swizzle[i]; + } + } + if (alu.type == BI_CSEL) { /* Default to csel3 */ alu.cond = BI_COND_NE; -- 2.7.4