From a176d60f9d8fab161a44994bbd37b883d995e428 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Tue, 5 Jun 2007 12:54:41 +0000 Subject: [PATCH] constraints.md ("Y2"): Replaced by ... 2007-06-05 H.J. Lu * config/i386/constraints.md ("Y2"): Replaced by ... ("Yt"): This. * config/i386/i386.md: Likewise. * config/i386/mmx.md: Likewise. * config/i386/sse.md: Likewise. From-SVN: r125333 --- gcc/ChangeLog | 8 ++++++++ gcc/config/i386/constraints.md | 4 ++-- gcc/config/i386/i386.md | 32 ++++++++++++++++---------------- gcc/config/i386/mmx.md | 20 ++++++++++---------- gcc/config/i386/sse.md | 26 +++++++++++++------------- 5 files changed, 49 insertions(+), 41 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index fee898b..4ea1037 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,13 @@ 2007-06-05 H.J. Lu + * config/i386/constraints.md ("Y2"): Replaced by ... + ("Yt"): This. + * config/i386/i386.md: Likewise. + * config/i386/mmx.md: Likewise. + * config/i386/sse.md: Likewise. + +2007-06-05 H.J. Lu + * config/i386/constraints.md ("z"): Replaced by ... ("Y0"): This. * config/i386/sse.md (sse4_1_blendvpd): Likewise. diff --git a/gcc/config/i386/constraints.md b/gcc/config/i386/constraints.md index 452bc42..70a0ad0 100644 --- a/gcc/config/i386/constraints.md +++ b/gcc/config/i386/constraints.md @@ -85,14 +85,14 @@ ;; We use the Y prefix to denote any number of conditional register sets: ;; 0 First SSE register. -;; 2 SSE2 enabled +;; t SSE2 enabled ;; i SSE2 inter-unit moves enabled ;; m MMX inter-unit moves enabled (define_register_constraint "Y0" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS" "First SSE register (@code{%xmm0}).") -(define_register_constraint "Y2" "TARGET_SSE2 ? SSE_REGS : NO_REGS" +(define_register_constraint "Yt" "TARGET_SSE2 ? SSE_REGS : NO_REGS" "@internal Any SSE register, when SSE2 is enabled.") (define_register_constraint "Yi" diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 3d10177..3e9a15f 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -1987,9 +1987,9 @@ (define_insn "*movdi_2" [(set (match_operand:DI 0 "nonimmediate_operand" - "=r ,o ,*y,m*y,*y,*Y2,m ,*Y2,*Y2,*x,m ,*x,*x") + "=r ,o ,*y,m*y,*y,*Yt,m ,*Yt,*Yt,*x,m ,*x,*x") (match_operand:DI 1 "general_operand" - "riFo,riF,C ,*y ,m ,C ,*Y2,*Y2,m ,C ,*x,*x,m "))] + "riFo,riF,C ,*y ,m ,C ,*Yt,*Yt,m ,C ,*x,*x,m "))] "!TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))" "@ # @@ -2460,7 +2460,7 @@ (define_insn "*pushdf_nointeger" [(set (match_operand:DF 0 "push_operand" "=<,<,<,<") - (match_operand:DF 1 "general_no_elim_operand" "f,Fo,*r,Y2"))] + (match_operand:DF 1 "general_no_elim_operand" "f,Fo,*r,Yt"))] "!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES" { /* This insn should be already split before reg-stack. */ @@ -2472,7 +2472,7 @@ (define_insn "*pushdf_integer" [(set (match_operand:DF 0 "push_operand" "=<,<,<") - (match_operand:DF 1 "general_no_elim_operand" "f,rFo,Y2"))] + (match_operand:DF 1 "general_no_elim_operand" "f,rFo,Yt"))] "TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES" { /* This insn should be already split before reg-stack. */ @@ -2512,9 +2512,9 @@ (define_insn "*movdf_nointeger" [(set (match_operand:DF 0 "nonimmediate_operand" - "=f,m,f,*r ,o ,Y2*x,Y2*x,Y2*x ,m ") + "=f,m,f,*r ,o ,Yt*x,Yt*x,Yt*x ,m ") (match_operand:DF 1 "general_operand" - "fm,f,G,*roF,F*r,C ,Y2*x,mY2*x,Y2*x"))] + "fm,f,G,*roF,F*r,C ,Yt*x,mYt*x,Yt*x"))] "!(MEM_P (operands[0]) && MEM_P (operands[1])) && ((optimize_size || !TARGET_INTEGER_DFMODE_MOVES) && !TARGET_64BIT) && (reload_in_progress || reload_completed @@ -2629,9 +2629,9 @@ (define_insn "*movdf_integer_rex64" [(set (match_operand:DF 0 "nonimmediate_operand" - "=f,m,f,r ,m ,Y2*x,Y2*x,Y2*x,m ,Yi,r ") + "=f,m,f,r ,m ,Yt*x,Yt*x,Yt*x,m ,Yi,r ") (match_operand:DF 1 "general_operand" - "fm,f,G,rmF,Fr,C ,Y2*x,m ,Y2*x,r ,Yi"))] + "fm,f,G,rmF,Fr,C ,Yt*x,m ,Yt*x,r ,Yi"))] "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1])) && (reload_in_progress || reload_completed || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE) @@ -2750,9 +2750,9 @@ (define_insn "*movdf_integer" [(set (match_operand:DF 0 "nonimmediate_operand" - "=f,m,f,r ,o ,Y2*x,Y2*x,Y2*x,m ") + "=f,m,f,r ,o ,Yt*x,Yt*x,Yt*x,m ") (match_operand:DF 1 "general_operand" - "fm,f,G,roF,Fr,C ,Y2*x,m ,Y2*x"))] + "fm,f,G,roF,Fr,C ,Yt*x,m ,Yt*x"))] "!(MEM_P (operands[0]) && MEM_P (operands[1])) && !optimize_size && TARGET_INTEGER_DFMODE_MOVES && (reload_in_progress || reload_completed @@ -3386,7 +3386,7 @@ }) (define_insn "zero_extendsidi2_32" - [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?o,?*Ym,?*y,?*Yi,*Y2") + [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?o,?*Ym,?*y,?*Yi,*Yt") (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r ,r ,m ,r ,m"))) (clobber (reg:CC FLAGS_REG))] @@ -3403,7 +3403,7 @@ (set_attr "type" "multi,multi,multi,mmxmov,mmxmov,ssemov,ssemov")]) (define_insn "zero_extendsidi2_rex64" - [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,?*Ym,?*y,?*Yi,*Y2") + [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,?*Ym,?*y,?*Yi,*Yt") (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0,r ,m ,r ,m")))] "TARGET_64BIT" @@ -3906,9 +3906,9 @@ (set_attr "mode" "SF")]) (define_insn "*truncdfsf_mixed" - [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?fx*r,Y2") + [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?fx*r,Yt") (float_truncate:SF - (match_operand:DF 1 "nonimmediate_operand" "f ,f ,Y2m"))) + (match_operand:DF 1 "nonimmediate_operand" "f ,f ,Ytm"))) (clobber (match_operand:SF 2 "memory_operand" "=X,m ,X"))] "TARGET_MIX_SSE_I387" { @@ -4010,7 +4010,7 @@ (set_attr "mode" "SF")]) (define_insn "*truncxfdf2_mixed" - [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?fY2*r") + [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?fYt*r") (float_truncate:DF (match_operand:XF 1 "register_operand" "f,f"))) (clobber (match_operand:DF 2 "memory_operand" "=X,m"))] @@ -4237,7 +4237,7 @@ ;; Avoid vector decoded forms of the instruction. (define_peephole2 - [(match_scratch:DF 2 "Y2") + [(match_scratch:DF 2 "Yt") (set (match_operand:SSEMODEI24 0 "register_operand" "") (fix:SSEMODEI24 (match_operand:DF 1 "memory_operand" "")))] "TARGET_AVOID_VECTOR_DECODE && !optimize_size" diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 3766d08..ac4721b 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -64,9 +64,9 @@ (define_insn "*mov_internal_rex64" [(set (match_operand:MMXMODEI 0 "nonimmediate_operand" - "=rm,r,*y,*y ,m ,*y,Y2,x,x ,m,r,x") + "=rm,r,*y,*y ,m ,*y,Yt,x,x ,m,r,x") (match_operand:MMXMODEI 1 "vector_move_operand" - "Cr ,m,C ,*ym,*y,Y2,*y,C,xm,x,x,r"))] + "Cr ,m,C ,*ym,*y,Yt,*y,C,xm,x,x,r"))] "TARGET_64BIT && TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))" "@ @@ -88,9 +88,9 @@ (define_insn "*mov_internal" [(set (match_operand:MMXMODEI 0 "nonimmediate_operand" - "=*y,*y ,m ,*y ,*Y2,*Y2,*Y2 ,m ,*x,*x,*x,m ,?r ,?m") + "=*y,*y ,m ,*y ,*Yt,*Yt,*Yt ,m ,*x,*x,*x,m ,?r ,?m") (match_operand:MMXMODEI 1 "vector_move_operand" - "C ,*ym,*y,*Y2,*y ,C ,*Y2m,*Y2,C ,*x,m ,*x,irm,r"))] + "C ,*ym,*y,*Yt,*y ,C ,*Ytm,*Yt,C ,*x,m ,*x,irm,r"))] "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))" "@ @@ -123,9 +123,9 @@ (define_insn "*movv2sf_internal_rex64" [(set (match_operand:V2SF 0 "nonimmediate_operand" - "=rm,r,*y ,*y ,m ,*y,Y2,x,x,x,m,r,x") + "=rm,r,*y ,*y ,m ,*y,Yt,x,x,x,m,r,x") (match_operand:V2SF 1 "vector_move_operand" - "Cr ,m ,C ,*ym,*y,Y2,*y,C,x,m,x,x,r"))] + "Cr ,m ,C ,*ym,*y,Yt,*y,C,x,m,x,x,r"))] "TARGET_64BIT && TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))" "@ @@ -148,9 +148,9 @@ (define_insn "*movv2sf_internal" [(set (match_operand:V2SF 0 "nonimmediate_operand" - "=*y,*y ,m,*y ,*Y2,*x,*x,*x,m ,?r ,?m") + "=*y,*y ,m,*y ,*Yt,*x,*x,*x,m ,?r ,?m") (match_operand:V2SF 1 "vector_move_operand" - "C ,*ym,*y,*Y2,*y ,C ,*x,m ,*x,irm,r"))] + "C ,*ym,*y,*Yt,*y ,C ,*x,m ,*x,irm,r"))] "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))" "@ @@ -1172,9 +1172,9 @@ }) (define_insn "*vec_extractv2si_1" - [(set (match_operand:SI 0 "nonimmediate_operand" "=y,Y2,Y2,x,frxy") + [(set (match_operand:SI 0 "nonimmediate_operand" "=y,Yt,Yt,x,frxy") (vec_select:SI - (match_operand:V2SI 1 "nonimmediate_operand" " 0,0 ,Y2,0,o") + (match_operand:V2SI 1 "nonimmediate_operand" " 0,0 ,Yt,0,o") (parallel [(const_int 1)])))] "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))" "@ diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index a6c6ad8..bdb653d 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -1364,7 +1364,7 @@ }) (define_insn "vec_setv4sf_0" - [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,Y2,m") + [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,Yt,m") (vec_merge:V4SF (vec_duplicate:V4SF (match_operand:SF 2 "general_operand" " x,m,*r,x*rfF")) @@ -2645,10 +2645,10 @@ (set_attr "mode" "DF")]) (define_insn "*vec_concatv2df" - [(set (match_operand:V2DF 0 "register_operand" "=Y2,Y2,Y2,x,x") + [(set (match_operand:V2DF 0 "register_operand" "=Yt,Yt,Yt,x,x") (vec_concat:V2DF (match_operand:DF 1 "nonimmediate_operand" " 0 ,0 ,m ,0,0") - (match_operand:DF 2 "vector_move_operand" " Y2,m ,C ,x,m")))] + (match_operand:DF 2 "vector_move_operand" " Yt,m ,C ,x,m")))] "TARGET_SSE" "@ unpcklpd\t{%2, %0|%0, %2} @@ -4422,7 +4422,7 @@ "operands[2] = CONST0_RTX (V4SImode);") (define_insn "sse2_loadld" - [(set (match_operand:V4SI 0 "register_operand" "=Y2,Yi,x,x") + [(set (match_operand:V4SI 0 "register_operand" "=Yt,Yi,x,x") (vec_merge:V4SI (vec_duplicate:V4SI (match_operand:SI 2 "nonimmediate_operand" "m ,r ,m,x")) @@ -4522,9 +4522,9 @@ (set_attr "mode" "V2SF,V4SF,V2SF")]) (define_insn "*vec_dupv4si" - [(set (match_operand:V4SI 0 "register_operand" "=Y2,x") + [(set (match_operand:V4SI 0 "register_operand" "=Yt,x") (vec_duplicate:V4SI - (match_operand:SI 1 "register_operand" " Y2,0")))] + (match_operand:SI 1 "register_operand" " Yt,0")))] "TARGET_SSE" "@ pshufd\t{$0, %1, %0|%0, %1, 0} @@ -4533,7 +4533,7 @@ (set_attr "mode" "TI,V4SF")]) (define_insn "*vec_dupv2di" - [(set (match_operand:V2DI 0 "register_operand" "=Y2,x") + [(set (match_operand:V2DI 0 "register_operand" "=Yt,x") (vec_duplicate:V2DI (match_operand:DI 1 "register_operand" " 0 ,0")))] "TARGET_SSE" @@ -4547,10 +4547,10 @@ ;; nonimmediate_operand for operand 2 and *not* allowing memory for the SSE ;; alternatives pretty much forces the MMX alternative to be chosen. (define_insn "*sse2_concatv2si" - [(set (match_operand:V2SI 0 "register_operand" "=Y2, Y2,*y,*y") + [(set (match_operand:V2SI 0 "register_operand" "=Yt, Yt,*y,*y") (vec_concat:V2SI (match_operand:SI 1 "nonimmediate_operand" " 0 ,rm , 0,rm") - (match_operand:SI 2 "reg_or_0_operand" " Y2,C ,*y, C")))] + (match_operand:SI 2 "reg_or_0_operand" " Yt,C ,*y, C")))] "TARGET_SSE2" "@ punpckldq\t{%2, %0|%0, %2} @@ -4575,10 +4575,10 @@ (set_attr "mode" "V4SF,V4SF,DI,DI")]) (define_insn "*vec_concatv4si_1" - [(set (match_operand:V4SI 0 "register_operand" "=Y2,x,x") + [(set (match_operand:V4SI 0 "register_operand" "=Yt,x,x") (vec_concat:V4SI (match_operand:V2SI 1 "register_operand" " 0 ,0,0") - (match_operand:V2SI 2 "nonimmediate_operand" " Y2,x,m")))] + (match_operand:V2SI 2 "nonimmediate_operand" " Yt,x,m")))] "TARGET_SSE" "@ punpcklqdq\t{%2, %0|%0, %2} @@ -4588,10 +4588,10 @@ (set_attr "mode" "TI,V4SF,V2SF")]) (define_insn "vec_concatv2di" - [(set (match_operand:V2DI 0 "register_operand" "=Y2,?Y2,Y2,x,x,x") + [(set (match_operand:V2DI 0 "register_operand" "=Yt,?Yt,Yt,x,x,x") (vec_concat:V2DI (match_operand:DI 1 "nonimmediate_operand" " m,*y ,0 ,0,0,m") - (match_operand:DI 2 "vector_move_operand" " C, C,Y2,x,m,0")))] + (match_operand:DI 2 "vector_move_operand" " C, C,Yt,x,m,0")))] "TARGET_SSE" "@ movq\t{%1, %0|%0, %1} -- 2.7.4