From a1155ae64dc7f3672e81ff7db4f58a371d36e9f0 Mon Sep 17 00:00:00 2001 From: Ayke van Laethem Date: Mon, 22 Feb 2021 01:36:26 +0100 Subject: [PATCH] [AVR] Fix lifeness issues in the AVR backend This patch is a large number of small changes that should hopefully not affect the generated machine code but are still important to get right so that the machine verifier won't complain about them. The llvm/test/CodeGen/AVR/pseudo/*.mir changes are also necessary because without the liveins the used registers are considered undefined by the machine verifier and it will complain about them. Differential Revision: https://reviews.llvm.org/D97172 --- llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp | 29 ++++++++++++---------- llvm/lib/Target/AVR/AVRFrameLowering.cpp | 2 +- llvm/test/CodeGen/AVR/pseudo/ADCWRdRr.mir | 1 + llvm/test/CodeGen/AVR/pseudo/ADDWRdRr.mir | 1 + llvm/test/CodeGen/AVR/pseudo/ANDIWRdK.mir | 1 + llvm/test/CodeGen/AVR/pseudo/ANDWRdRr.mir | 1 + llvm/test/CodeGen/AVR/pseudo/ASRWRd.mir | 1 + llvm/test/CodeGen/AVR/pseudo/COMWRd.mir | 1 + llvm/test/CodeGen/AVR/pseudo/CPCWRdRr.mir | 1 + llvm/test/CodeGen/AVR/pseudo/CPWRdRr.mir | 1 + llvm/test/CodeGen/AVR/pseudo/EORWRdRr.mir | 1 + llvm/test/CodeGen/AVR/pseudo/FRMIDX.mir | 1 + llvm/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir | 1 + .../CodeGen/AVR/pseudo/LDWRdPtr-same-src-dst.mir | 1 + llvm/test/CodeGen/AVR/pseudo/LDWRdPtr.mir | 1 + llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir | 1 + llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir | 1 + llvm/test/CodeGen/AVR/pseudo/LSLWRd.mir | 1 + llvm/test/CodeGen/AVR/pseudo/LSRWRd.mir | 1 + llvm/test/CodeGen/AVR/pseudo/NEGWRd.mir | 1 + llvm/test/CodeGen/AVR/pseudo/ORIWRdK.mir | 1 + llvm/test/CodeGen/AVR/pseudo/ORWRdRr.mir | 1 + llvm/test/CodeGen/AVR/pseudo/OUTWARr.mir | 1 + llvm/test/CodeGen/AVR/pseudo/SBCIWRdK.mir | 1 + llvm/test/CodeGen/AVR/pseudo/SBCWRdRr.mir | 1 + llvm/test/CodeGen/AVR/pseudo/SEXT.mir | 1 + llvm/test/CodeGen/AVR/pseudo/STSWKRr.mir | 1 + llvm/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir | 1 + llvm/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir | 1 + llvm/test/CodeGen/AVR/pseudo/STWPtrRr.mir | 1 + llvm/test/CodeGen/AVR/pseudo/SUBIWRdK.mir | 1 + llvm/test/CodeGen/AVR/pseudo/SUBWRdRr.mir | 1 + llvm/test/CodeGen/AVR/pseudo/ZEXT.mir | 1 + 33 files changed, 48 insertions(+), 14 deletions(-) diff --git a/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp b/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp index 8fb020c..7aebf9a 100644 --- a/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp +++ b/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp @@ -1055,6 +1055,7 @@ bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) { Register SrcLoReg, SrcHiReg; Register DstReg = MI.getOperand(0).getReg(); Register SrcReg = MI.getOperand(1).getReg(); + bool DstIsUndef = MI.getOperand(0).isUndef(); bool SrcIsKill = MI.getOperand(1).isKill(); unsigned OpLo = AVR::STPtrRr; unsigned OpHi = AVR::STDPtrQRr; @@ -1062,11 +1063,11 @@ bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) { //:TODO: need to reverse this order like inw and stsw? auto MIBLO = buildMI(MBB, MBBI, OpLo) - .addReg(DstReg) + .addReg(DstReg, getUndefRegState(DstIsUndef)) .addReg(SrcLoReg, getKillRegState(SrcIsKill)); auto MIBHI = buildMI(MBB, MBBI, OpHi) - .addReg(DstReg) + .addReg(DstReg, getUndefRegState(DstIsUndef)) .addImm(1) .addReg(SrcHiReg, getKillRegState(SrcIsKill)); @@ -1435,7 +1436,7 @@ bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) { buildMI(MBB, MBBI, AVR::EORRdRr) .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) .addReg(DstHiReg, getKillRegState(DstIsKill)) - .addReg(DstLoReg, getKillRegState(DstIsKill)); + .addReg(DstLoReg); // SREG is implicitly dead. MI1->getOperand(3).setIsDead(); @@ -1453,7 +1454,7 @@ bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) { buildMI(MBB, MBBI, AVR::EORRdRr) .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) .addReg(DstHiReg, getKillRegState(DstIsKill)) - .addReg(DstLoReg, getKillRegState(DstIsKill)); + .addReg(DstLoReg); if (ImpIsDead) MI3->getOperand(3).setIsDead(); @@ -1474,7 +1475,7 @@ bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) { // mov Rh, Rl buildMI(MBB, MBBI, AVR::MOVRdRr) .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) - .addReg(DstLoReg, getKillRegState(DstIsKill)); + .addReg(DstLoReg); // clr Rl auto MIBLO = @@ -1502,7 +1503,7 @@ bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) { // mov Rh, Rl buildMI(MBB, MBBI, AVR::MOVRdRr) .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) - .addReg(DstLoReg, getKillRegState(DstIsKill)); + .addReg(DstLoReg); // swap Rh buildMI(MBB, MBBI, AVR::SWAPRd) @@ -1595,7 +1596,7 @@ bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) { buildMI(MBB, MBBI, AVR::EORRdRr) .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) .addReg(DstLoReg, getKillRegState(DstIsKill)) - .addReg(DstHiReg, getKillRegState(DstIsKill)); + .addReg(DstHiReg); // SREG is implicitly dead. MI1->getOperand(3).setIsDead(); @@ -1613,7 +1614,7 @@ bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) { buildMI(MBB, MBBI, AVR::EORRdRr) .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) .addReg(DstLoReg, getKillRegState(DstIsKill)) - .addReg(DstHiReg, getKillRegState(DstIsKill)); + .addReg(DstHiReg); if (ImpIsDead) MI3->getOperand(3).setIsDead(); @@ -1747,7 +1748,7 @@ bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) { // Move upper byte to lower byte. buildMI(MBB, MBBI, AVR::MOVRdRr) .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) - .addReg(DstHiReg, getKillRegState(DstIsKill)); + .addReg(DstHiReg); // Move the sign bit to the C flag. buildMI(MBB, MBBI, AVR::ADDRdRr) @@ -1782,7 +1783,8 @@ bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) { buildMI(MBB, MBBI, AVR::RORRd) .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) - .addReg(DstReg, getKillRegState(DstIsKill)); + .addReg(DstReg, getKillRegState(DstIsKill)) + ->getOperand(3).setIsUndef(true); buildMI(MBB, MBBI, AVR::EORRdRr) .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) @@ -1819,7 +1821,8 @@ bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) { buildMI(MBB, MBBI, AVR::ADCRdRr) .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) .addReg(DstReg, getKillRegState(DstIsKill)) - .addReg(DstReg, getKillRegState(DstIsKill)); + .addReg(DstReg, getKillRegState(DstIsKill)) + ->getOperand(4).setIsUndef(true); buildMI(MBB, MBBI, AVR::EORRdRr) .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) @@ -1958,8 +1961,8 @@ template <> bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) { auto EOR = buildMI(MBB, MBBI, AVR::EORRdRr) .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) - .addReg(DstHiReg, RegState::Kill) - .addReg(DstHiReg, RegState::Kill); + .addReg(DstHiReg, RegState::Kill | RegState::Undef) + .addReg(DstHiReg, RegState::Kill | RegState::Undef); if (ImpIsDead) EOR->getOperand(3).setIsDead(); diff --git a/llvm/lib/Target/AVR/AVRFrameLowering.cpp b/llvm/lib/Target/AVR/AVRFrameLowering.cpp index 757b414..e998010 100644 --- a/llvm/lib/Target/AVR/AVRFrameLowering.cpp +++ b/llvm/lib/Target/AVR/AVRFrameLowering.cpp @@ -362,7 +362,7 @@ MachineBasicBlock::iterator AVRFrameLowering::eliminateCallFramePseudoInstr( New->getOperand(3).setIsDead(); BuildMI(MBB, MI, DL, TII.get(AVR::SPWRITE), AVR::SP) - .addReg(AVR::R31R30, RegState::Kill); + .addReg(AVR::R31R30); // Make sure the remaining stack stores are converted to real store // instructions. diff --git a/llvm/test/CodeGen/AVR/pseudo/ADCWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/ADCWRdRr.mir index aa10f6a..2626399 100644 --- a/llvm/test/CodeGen/AVR/pseudo/ADCWRdRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/ADCWRdRr.mir @@ -14,6 +14,7 @@ name: test_adcwrdrr body: | bb.0.entry: + liveins: $r15r14, $r21r20, $sreg ; CHECK-LABEL: test_adcwrdrr diff --git a/llvm/test/CodeGen/AVR/pseudo/ADDWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/ADDWRdRr.mir index a8cd4b4..1dfa417 100644 --- a/llvm/test/CodeGen/AVR/pseudo/ADDWRdRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/ADDWRdRr.mir @@ -14,6 +14,7 @@ name: test_addwrdrr body: | bb.0.entry: + liveins: $r15r14, $r21r20 ; CHECK-LABEL: test_addwrdrr diff --git a/llvm/test/CodeGen/AVR/pseudo/ANDIWRdK.mir b/llvm/test/CodeGen/AVR/pseudo/ANDIWRdK.mir index 340c7c3..94d580b 100644 --- a/llvm/test/CodeGen/AVR/pseudo/ANDIWRdK.mir +++ b/llvm/test/CodeGen/AVR/pseudo/ANDIWRdK.mir @@ -14,6 +14,7 @@ name: test_andiwrdrr body: | bb.0.entry: + liveins: $r17r16 ; CHECK-LABEL: test_andiwrdrr diff --git a/llvm/test/CodeGen/AVR/pseudo/ANDWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/ANDWRdRr.mir index b3bc6a8..98295d0 100644 --- a/llvm/test/CodeGen/AVR/pseudo/ANDWRdRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/ANDWRdRr.mir @@ -14,6 +14,7 @@ name: test_andwrdrr body: | bb.0.entry: + liveins: $r15r14, $r21r20 ; CHECK-LABEL: test_andwrdrr diff --git a/llvm/test/CodeGen/AVR/pseudo/ASRWRd.mir b/llvm/test/CodeGen/AVR/pseudo/ASRWRd.mir index e364d81..79b6929 100644 --- a/llvm/test/CodeGen/AVR/pseudo/ASRWRd.mir +++ b/llvm/test/CodeGen/AVR/pseudo/ASRWRd.mir @@ -12,6 +12,7 @@ name: test body: | bb.0.entry: + liveins: $r15r14 ; CHECK-LABEL: test diff --git a/llvm/test/CodeGen/AVR/pseudo/COMWRd.mir b/llvm/test/CodeGen/AVR/pseudo/COMWRd.mir index 4718d7d..bd3ce4c 100644 --- a/llvm/test/CodeGen/AVR/pseudo/COMWRd.mir +++ b/llvm/test/CodeGen/AVR/pseudo/COMWRd.mir @@ -14,6 +14,7 @@ name: test_comwrd body: | bb.0.entry: + liveins: $r15r14 ; CHECK-LABEL: test_comwrd diff --git a/llvm/test/CodeGen/AVR/pseudo/CPCWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/CPCWRdRr.mir index 2ed3d10..d51a757 100644 --- a/llvm/test/CodeGen/AVR/pseudo/CPCWRdRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/CPCWRdRr.mir @@ -14,6 +14,7 @@ name: test_cpcwrdrr body: | bb.0.entry: + liveins: $r21r20, $r23r22, $sreg ; CHECK-LABEL: test_cpcwrdrr diff --git a/llvm/test/CodeGen/AVR/pseudo/CPWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/CPWRdRr.mir index 62069a7..bb9f8cb 100644 --- a/llvm/test/CodeGen/AVR/pseudo/CPWRdRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/CPWRdRr.mir @@ -14,6 +14,7 @@ name: test_cpwrdrr body: | bb.0.entry: + liveins: $r15r14, $r21r20 ; CHECK-LABEL: test_cpwrdrr diff --git a/llvm/test/CodeGen/AVR/pseudo/EORWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/EORWRdRr.mir index 3ff829a..9ff4e55 100644 --- a/llvm/test/CodeGen/AVR/pseudo/EORWRdRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/EORWRdRr.mir @@ -14,6 +14,7 @@ name: test_eorwrdrr body: | bb.0.entry: + liveins: $r15r14, $r21r20 ; CHECK-LABEL: test_eorwrdrr diff --git a/llvm/test/CodeGen/AVR/pseudo/FRMIDX.mir b/llvm/test/CodeGen/AVR/pseudo/FRMIDX.mir index 8815802..f45eeb6 100644 --- a/llvm/test/CodeGen/AVR/pseudo/FRMIDX.mir +++ b/llvm/test/CodeGen/AVR/pseudo/FRMIDX.mir @@ -18,6 +18,7 @@ registers: - { id: 0, class: _ } body: | bb.0.entry: + liveins: $r31r30 ; CHECK-LABEL: test diff --git a/llvm/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir b/llvm/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir index ef8519e..d13bf11 100644 --- a/llvm/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir +++ b/llvm/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir @@ -15,6 +15,7 @@ name: test_lddwrdptrq tracksRegLiveness: true body: | bb.0.entry: + liveins: $r31r30 ; CHECK-LABEL: test_lddwrdptrq diff --git a/llvm/test/CodeGen/AVR/pseudo/LDWRdPtr-same-src-dst.mir b/llvm/test/CodeGen/AVR/pseudo/LDWRdPtr-same-src-dst.mir index 3c3a721..9ceef4c 100644 --- a/llvm/test/CodeGen/AVR/pseudo/LDWRdPtr-same-src-dst.mir +++ b/llvm/test/CodeGen/AVR/pseudo/LDWRdPtr-same-src-dst.mir @@ -15,6 +15,7 @@ name: test_ldwrdptr tracksRegLiveness: true body: | bb.0.entry: + liveins: $r31r30 ; CHECK-LABEL: test_ldwrdptr diff --git a/llvm/test/CodeGen/AVR/pseudo/LDWRdPtr.mir b/llvm/test/CodeGen/AVR/pseudo/LDWRdPtr.mir index 2343d0d..d86b60b 100644 --- a/llvm/test/CodeGen/AVR/pseudo/LDWRdPtr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/LDWRdPtr.mir @@ -14,6 +14,7 @@ name: test_ldwrdptr body: | bb.0.entry: + liveins: $r31r30 ; CHECK-LABEL: test_ldwrdptr diff --git a/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir b/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir index 39abc45..56623ec 100644 --- a/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir +++ b/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir @@ -14,6 +14,7 @@ name: test_ldwrdptrpd body: | bb.0.entry: + liveins: $r31r30 ; CHECK-LABEL: test_ldwrdptrpd diff --git a/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir b/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir index 42c255a..98429a4 100644 --- a/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir +++ b/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir @@ -14,6 +14,7 @@ name: test_ldwrdptrpi body: | bb.0.entry: + liveins: $r31r30 ; CHECK-LABEL: test_ldwrdptrpi diff --git a/llvm/test/CodeGen/AVR/pseudo/LSLWRd.mir b/llvm/test/CodeGen/AVR/pseudo/LSLWRd.mir index b260e70..b1b9f1f 100644 --- a/llvm/test/CodeGen/AVR/pseudo/LSLWRd.mir +++ b/llvm/test/CodeGen/AVR/pseudo/LSLWRd.mir @@ -12,6 +12,7 @@ name: test body: | bb.0.entry: + liveins: $r15r14 ; CHECK-LABEL: test diff --git a/llvm/test/CodeGen/AVR/pseudo/LSRWRd.mir b/llvm/test/CodeGen/AVR/pseudo/LSRWRd.mir index d3bee8bb..d7fabf6 100644 --- a/llvm/test/CodeGen/AVR/pseudo/LSRWRd.mir +++ b/llvm/test/CodeGen/AVR/pseudo/LSRWRd.mir @@ -12,6 +12,7 @@ name: test body: | bb.0.entry: + liveins: $r15r14 ; CHECK-LABEL: test diff --git a/llvm/test/CodeGen/AVR/pseudo/NEGWRd.mir b/llvm/test/CodeGen/AVR/pseudo/NEGWRd.mir index 5cf947e..71ed9a4 100644 --- a/llvm/test/CodeGen/AVR/pseudo/NEGWRd.mir +++ b/llvm/test/CodeGen/AVR/pseudo/NEGWRd.mir @@ -14,6 +14,7 @@ name: test_negwrd body: | bb.0.entry: + liveins: $r15r14 ; CHECK-LABEL: test_negwrd diff --git a/llvm/test/CodeGen/AVR/pseudo/ORIWRdK.mir b/llvm/test/CodeGen/AVR/pseudo/ORIWRdK.mir index 568f8b99..169e644 100644 --- a/llvm/test/CodeGen/AVR/pseudo/ORIWRdK.mir +++ b/llvm/test/CodeGen/AVR/pseudo/ORIWRdK.mir @@ -14,6 +14,7 @@ name: test_oriwrdrr body: | bb.0.entry: + liveins: $r21r20 ; CHECK-LABEL: test_oriwrdrr diff --git a/llvm/test/CodeGen/AVR/pseudo/ORWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/ORWRdRr.mir index 6f4167b..eb2cea6a 100644 --- a/llvm/test/CodeGen/AVR/pseudo/ORWRdRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/ORWRdRr.mir @@ -14,6 +14,7 @@ name: test_orwrdrr body: | bb.0.entry: + liveins: $r15r14, $r21r20 ; CHECK-LABEL: test_orwrdrr diff --git a/llvm/test/CodeGen/AVR/pseudo/OUTWARr.mir b/llvm/test/CodeGen/AVR/pseudo/OUTWARr.mir index 53ed8cc..3152085 100644 --- a/llvm/test/CodeGen/AVR/pseudo/OUTWARr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/OUTWARr.mir @@ -12,6 +12,7 @@ name: test body: | bb.0.entry: + liveins: $r15r14 ; CHECK-LABEL: test diff --git a/llvm/test/CodeGen/AVR/pseudo/SBCIWRdK.mir b/llvm/test/CodeGen/AVR/pseudo/SBCIWRdK.mir index 8b8c462..303ee1f 100644 --- a/llvm/test/CodeGen/AVR/pseudo/SBCIWRdK.mir +++ b/llvm/test/CodeGen/AVR/pseudo/SBCIWRdK.mir @@ -14,6 +14,7 @@ name: test_sbciwrdk body: | bb.0.entry: + liveins: $r21r20, $sreg ; CHECK-LABEL: test_sbciwrdk diff --git a/llvm/test/CodeGen/AVR/pseudo/SBCWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/SBCWRdRr.mir index 9fbc6de..4e21ba1 100644 --- a/llvm/test/CodeGen/AVR/pseudo/SBCWRdRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/SBCWRdRr.mir @@ -14,6 +14,7 @@ name: test_sbcwrdrr body: | bb.0.entry: + liveins: $r15r14, $r21r20, $sreg ; CHECK-LABEL: test_sbcwrdrr diff --git a/llvm/test/CodeGen/AVR/pseudo/SEXT.mir b/llvm/test/CodeGen/AVR/pseudo/SEXT.mir index b7077a3..0411673 100644 --- a/llvm/test/CodeGen/AVR/pseudo/SEXT.mir +++ b/llvm/test/CodeGen/AVR/pseudo/SEXT.mir @@ -12,6 +12,7 @@ name: test body: | bb.0.entry: + liveins: $r31 ; CHECK-LABEL: test diff --git a/llvm/test/CodeGen/AVR/pseudo/STSWKRr.mir b/llvm/test/CodeGen/AVR/pseudo/STSWKRr.mir index 9302f15..96a648b 100644 --- a/llvm/test/CodeGen/AVR/pseudo/STSWKRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/STSWKRr.mir @@ -14,6 +14,7 @@ name: test_stswkrr body: | bb.0.entry: + liveins: $r31r30 ; CHECK-LABEL: test_stswkrr diff --git a/llvm/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir b/llvm/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir index c8a5eba..f255de3 100644 --- a/llvm/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir @@ -12,6 +12,7 @@ name: test body: | bb.0.entry: + liveins: $r31r30 ; CHECK-LABEL: test diff --git a/llvm/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir b/llvm/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir index 3d65cab..1f1a199 100644 --- a/llvm/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir @@ -12,6 +12,7 @@ name: test body: | bb.0.entry: + liveins: $r31r30 ; CHECK-LABEL: test diff --git a/llvm/test/CodeGen/AVR/pseudo/STWPtrRr.mir b/llvm/test/CodeGen/AVR/pseudo/STWPtrRr.mir index 3ed4a50..203eb6b 100644 --- a/llvm/test/CodeGen/AVR/pseudo/STWPtrRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/STWPtrRr.mir @@ -14,6 +14,7 @@ name: test_stwptrrr body: | bb.0.entry: + liveins: $r31r30, $r17r16 ; CHECK-LABEL: test_stwptrrr diff --git a/llvm/test/CodeGen/AVR/pseudo/SUBIWRdK.mir b/llvm/test/CodeGen/AVR/pseudo/SUBIWRdK.mir index 3ea833f..3d1628f 100644 --- a/llvm/test/CodeGen/AVR/pseudo/SUBIWRdK.mir +++ b/llvm/test/CodeGen/AVR/pseudo/SUBIWRdK.mir @@ -14,6 +14,7 @@ name: test_subiwrdrr body: | bb.0.entry: + liveins: $r21r20 ; CHECK-LABEL: test_subiwrdrr diff --git a/llvm/test/CodeGen/AVR/pseudo/SUBWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/SUBWRdRr.mir index 8503646..30e69ab 100644 --- a/llvm/test/CodeGen/AVR/pseudo/SUBWRdRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/SUBWRdRr.mir @@ -14,6 +14,7 @@ name: test_subwrdrr body: | bb.0.entry: + liveins: $r21r20, $r15r14 ; CHECK-LABEL: test_subwrdrr diff --git a/llvm/test/CodeGen/AVR/pseudo/ZEXT.mir b/llvm/test/CodeGen/AVR/pseudo/ZEXT.mir index b7077a3..0411673 100644 --- a/llvm/test/CodeGen/AVR/pseudo/ZEXT.mir +++ b/llvm/test/CodeGen/AVR/pseudo/ZEXT.mir @@ -12,6 +12,7 @@ name: test body: | bb.0.entry: + liveins: $r31 ; CHECK-LABEL: test -- 2.7.4