From a0bc67e555f404d0e7ddb2e78cb891d96eaf913d Mon Sep 17 00:00:00 2001 From: Brad Smith Date: Fri, 3 Jun 2022 18:15:12 -0400 Subject: [PATCH] [Hexagon] Enable IAS in the Hexagon backend Reviewed By: kparzysz Differential Revision: https://reviews.llvm.org/D123096 --- llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp | 1 - llvm/test/CodeGen/Hexagon/inline-asm-hexagon.ll | 2 +- llvm/test/CodeGen/Hexagon/inline-asm-i1.ll | 2 +- llvm/test/CodeGen/Hexagon/inline-asm-qv.ll | 2 +- llvm/test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll | 6 +++--- llvm/test/CodeGen/Hexagon/v6-inlasm1.ll | 2 +- llvm/test/CodeGen/Hexagon/v6-inlasm2.ll | 2 +- llvm/test/CodeGen/Hexagon/v6-inlasm3.ll | 2 +- llvm/test/CodeGen/Hexagon/v6vec-vprint.ll | 4 ++-- 9 files changed, 11 insertions(+), 12 deletions(-) diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp index e5e5d08..f3da675 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp @@ -34,5 +34,4 @@ HexagonMCAsmInfo::HexagonMCAsmInfo(const Triple &TT) { UsesELFSectionDirectiveForBSS = true; ExceptionsType = ExceptionHandling::DwarfCFI; UseLogicalShr = false; - UseIntegratedAssembler = false; } diff --git a/llvm/test/CodeGen/Hexagon/inline-asm-hexagon.ll b/llvm/test/CodeGen/Hexagon/inline-asm-hexagon.ll index 76d7ae6..c7c44a3 100644 --- a/llvm/test/CodeGen/Hexagon/inline-asm-hexagon.ll +++ b/llvm/test/CodeGen/Hexagon/inline-asm-hexagon.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -march=hexagon -no-integrated-as < %s | FileCheck %s target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/inline-asm-i1.ll b/llvm/test/CodeGen/Hexagon/inline-asm-i1.ll index cc1f4ce..ee5a415 100644 --- a/llvm/test/CodeGen/Hexagon/inline-asm-i1.ll +++ b/llvm/test/CodeGen/Hexagon/inline-asm-i1.ll @@ -1,6 +1,6 @@ ; RUN: llc -march=hexagon < %s | FileCheck %s ; CHECK: r[[REG0:[0-9]+]] = usr -; CHECK: [[REG0]] = insert(r{{[0-9]+}}, #1, #16) +; CHECK: [[REG0]] = insert(r{{[0-9]+}},#1,#16) target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/inline-asm-qv.ll b/llvm/test/CodeGen/Hexagon/inline-asm-qv.ll index 5e9d223..624ab99 100644 --- a/llvm/test/CodeGen/Hexagon/inline-asm-qv.ll +++ b/llvm/test/CodeGen/Hexagon/inline-asm-qv.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -march=hexagon -no-integrated-as < %s | FileCheck %s ; Check that constraints q and v are handled correctly. ; CHECK: q{{.}} = vgtw(v{{.}}.w,v{{.}}.w) diff --git a/llvm/test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll b/llvm/test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll index 33e148d..f42ecf7 100644 --- a/llvm/test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll +++ b/llvm/test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll @@ -1,9 +1,9 @@ ; RUN: llc -march=hexagon < %s | FileCheck %s ; CHECK: r0 = #24 -; CHECK-NEXT: r1 = +; CHECK: r1 = ; // R2 should be assigned a value from R3+. -; CHECK-NEXT: r2 = r{{[3-9]}} -; CHECK-NEXT: trap0 +; CHECK: r2 = r{{[3-9]}} +; CHECK: trap0 target datalayout = "e-m:e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-n16:32" target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/v6-inlasm1.ll b/llvm/test/CodeGen/Hexagon/v6-inlasm1.ll index 135d947..105dac8f 100644 --- a/llvm/test/CodeGen/Hexagon/v6-inlasm1.ll +++ b/llvm/test/CodeGen/Hexagon/v6-inlasm1.ll @@ -1,5 +1,5 @@ ; RUN: llc -march=hexagon -O2 -disable-hexagon-shuffle=1 < %s | FileCheck %s -; CHECK: vmemu(r{{[0-9]+}}) = v{{[0-9]*}}; +; CHECK: vmemu(r{{[0-9]+}}+#0) = v{{[0-9]*}} target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/v6-inlasm2.ll b/llvm/test/CodeGen/Hexagon/v6-inlasm2.ll index 5def2da..1e9d526 100644 --- a/llvm/test/CodeGen/Hexagon/v6-inlasm2.ll +++ b/llvm/test/CodeGen/Hexagon/v6-inlasm2.ll @@ -1,5 +1,5 @@ ; RUN: llc -march=hexagon -O2 -disable-hexagon-shuffle=1 < %s | FileCheck %s -; CHECK: vmemu(r{{[0-9]+}}) = v{{[0-9]*}}; +; CHECK: vmemu(r{{[0-9]}}+#0) = v{{[0-9]*}} target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/v6-inlasm3.ll b/llvm/test/CodeGen/Hexagon/v6-inlasm3.ll index 1f4b03c..b4b3055 100644 --- a/llvm/test/CodeGen/Hexagon/v6-inlasm3.ll +++ b/llvm/test/CodeGen/Hexagon/v6-inlasm3.ll @@ -1,5 +1,5 @@ ; RUN: llc -march=hexagon -O2 -disable-hexagon-shuffle=1 < %s | FileCheck %s -; CHECK: vmemu(r{{[0-9]+}}) = v{{[0-9]*}} +; CHECK: vmemu(r{{[0-9]}}+#0) = v{{[0-9]*}} target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/v6vec-vprint.ll b/llvm/test/CodeGen/Hexagon/v6vec-vprint.ll index 944d089..0f232e4 100644 --- a/llvm/test/CodeGen/Hexagon/v6vec-vprint.ll +++ b/llvm/test/CodeGen/Hexagon/v6vec-vprint.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print < %s | FileCheck --check-prefix=CHECK %s -; RUN: llc -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print -trace-hex-vector-stores-only < %s | FileCheck --check-prefix=VSTPRINT %s +; RUN: llc -no-integrated-as -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print < %s | FileCheck --check-prefix=CHECK %s +; RUN: llc -no-integrated-as -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print -trace-hex-vector-stores-only < %s | FileCheck --check-prefix=VSTPRINT %s ; generate .long XXXX which is a vector debug print instruction. ; CHECK: .long 0x1dffe0 ; CHECK: .long 0x1dffe0 -- 2.7.4