From a0b3a9391cd8cfff2ad1741f12e5ed10acc97869 Mon Sep 17 00:00:00 2001 From: Dmitry Preobrazhensky Date: Sat, 5 Dec 2020 13:41:27 +0300 Subject: [PATCH] [AMDGPU][MC] Improved diagnostics message for sym/expr operands See bug 48295 (https://bugs.llvm.org/show_bug.cgi?id=48295) Reviewers: rampitec Differential Revision: https://reviews.llvm.org/D92088 --- .../Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 35 +++++++---- llvm/test/MC/AMDGPU/ds-err.s | 2 +- llvm/test/MC/AMDGPU/gfx10_err_pos.s | 68 +++++++++++++++------- llvm/test/MC/AMDGPU/sopk-err.s | 4 +- llvm/test/MC/AMDGPU/sopp-err.s | 8 +-- 5 files changed, 80 insertions(+), 37 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp index 8128bbc..4577493 100644 --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -1438,7 +1438,7 @@ private: void peekTokens(MutableArrayRef Tokens); AsmToken::TokenKind getTokenKind() const; - bool parseExpr(int64_t &Imm); + bool parseExpr(int64_t &Imm, StringRef Expected = ""); bool parseExpr(OperandVector &Operands); StringRef getTokenStr() const; AsmToken peekToken(); @@ -5683,8 +5683,8 @@ AMDGPUAsmParser::parseHwregBody(OperandInfoTy &HwReg, if (isToken(AsmToken::Identifier) && (HwReg.Id = getHwregId(getTokenStr())) >= 0) { HwReg.IsSymbolic = true; - lex(); // skip message name - } else if (!parseExpr(HwReg.Id)) { + lex(); // skip register name + } else if (!parseExpr(HwReg.Id, "a register name")) { return false; } @@ -5753,7 +5753,7 @@ AMDGPUAsmParser::parseHwreg(OperandVector &Operands) { } else { return MatchOperand_ParseFail; } - } else if (parseExpr(ImmVal)) { + } else if (parseExpr(ImmVal, "a hwreg macro")) { if (ImmVal < 0 || !isUInt<16>(ImmVal)) { Error(Loc, "invalid immediate: only 16-bit values are legal"); return MatchOperand_ParseFail; @@ -5784,7 +5784,7 @@ AMDGPUAsmParser::parseSendMsgBody(OperandInfoTy &Msg, if (isToken(AsmToken::Identifier) && (Msg.Id = getMsgId(getTokenStr())) >= 0) { Msg.IsSymbolic = true; lex(); // skip message name - } else if (!parseExpr(Msg.Id)) { + } else if (!parseExpr(Msg.Id, "a message name")) { return false; } @@ -5794,7 +5794,7 @@ AMDGPUAsmParser::parseSendMsgBody(OperandInfoTy &Msg, if (isToken(AsmToken::Identifier) && (Op.Id = getMsgOpId(Msg.Id, getTokenStr())) >= 0) { lex(); // skip operation name - } else if (!parseExpr(Op.Id)) { + } else if (!parseExpr(Op.Id, "an operation name")) { return false; } @@ -5864,7 +5864,7 @@ AMDGPUAsmParser::parseSendMsgOp(OperandVector &Operands) { } else { return MatchOperand_ParseFail; } - } else if (parseExpr(ImmVal)) { + } else if (parseExpr(ImmVal, "a sendmsg macro")) { if (ImmVal < 0 || !isUInt<16>(ImmVal)) { Error(Loc, "invalid immediate: only 16-bit values are legal"); return MatchOperand_ParseFail; @@ -6082,8 +6082,23 @@ AMDGPUAsmParser::skipToken(const AsmToken::TokenKind Kind, } bool -AMDGPUAsmParser::parseExpr(int64_t &Imm) { - return !getParser().parseAbsoluteExpression(Imm); +AMDGPUAsmParser::parseExpr(int64_t &Imm, StringRef Expected) { + SMLoc S = getLoc(); + + const MCExpr *Expr; + if (Parser.parseExpression(Expr)) + return false; + + if (Expr->evaluateAsAbsolute(Imm)) + return true; + + if (Expected.empty()) { + Error(S, "expected absolute expression"); + } else { + Error(S, Twine("expected ", Expected) + + Twine(" or an absolute expression")); + } + return false; } bool @@ -6400,7 +6415,7 @@ AMDGPUAsmParser::parseSwizzleOffset(int64_t &Imm) { SMLoc OffsetLoc = Parser.getTok().getLoc(); - if (!parseExpr(Imm)) { + if (!parseExpr(Imm, "a swizzle macro")) { return false; } if (!isUInt<16>(Imm)) { diff --git a/llvm/test/MC/AMDGPU/ds-err.s b/llvm/test/MC/AMDGPU/ds-err.s index 507bcbc..5d0a746 100644 --- a/llvm/test/MC/AMDGPU/ds-err.s +++ b/llvm/test/MC/AMDGPU/ds-err.s @@ -46,7 +46,7 @@ ds_swizzle_b32 v8, v2 offset: // CHECK: error: expected a colon ds_swizzle_b32 v8, v2 offset- -// CHECK: error: expected absolute expression +// CHECK: error: expected a swizzle macro or an absolute expression ds_swizzle_b32 v8, v2 offset:SWIZZLE(QUAD_PERM, 0, 1, 2, 3) // CHECK: error: expected a swizzle mode diff --git a/llvm/test/MC/AMDGPU/gfx10_err_pos.s b/llvm/test/MC/AMDGPU/gfx10_err_pos.s index f7c9bd9..8d0c369 100644 --- a/llvm/test/MC/AMDGPU/gfx10_err_pos.s +++ b/llvm/test/MC/AMDGPU/gfx10_err_pos.s @@ -331,26 +331,6 @@ ds_swizzle_b32 v8, v2 offset:swizzle(XXX,1) //============================================================================== // expected absolute expression -ds_swizzle_b32 v8, v2 offset:SWIZZLE(QUAD_PERM, 0, 1, 2, 3) -// CHECK: error: expected absolute expression -// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:SWIZZLE(QUAD_PERM, 0, 1, 2, 3) -// CHECK-NEXT:{{^}} ^ - -s_sendmsg sendmsg(MSG_GS, GS_OP_CUTX, 0) -// CHECK: error: expected absolute expression -// CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GS, GS_OP_CUTX, 0) -// CHECK-NEXT:{{^}} ^ - -s_sendmsg sendmsg(MSG_GSX, GS_OP_CUT, 0) -// CHECK: error: expected absolute expression -// CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GSX, GS_OP_CUT, 0) -// CHECK-NEXT:{{^}} ^ - -s_setreg_b32 hwreg(HW_REG_WRONG), s2 -// CHECK: error: expected absolute expression -// CHECK-NEXT:{{^}}s_setreg_b32 hwreg(HW_REG_WRONG), s2 -// CHECK-NEXT:{{^}} ^ - s_waitcnt vmcnt(x) // CHECK: error: expected absolute expression // CHECK-NEXT:{{^}}s_waitcnt vmcnt(x) @@ -372,6 +352,38 @@ tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:BUF_NUM_FORMAT_UINT] // CHECK-NEXT:{{^}} ^ //============================================================================== +// expected a message name or an absolute expression + +s_sendmsg sendmsg(MSG_GSX, GS_OP_CUT, 0) +// CHECK: error: expected a message name or an absolute expression +// CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GSX, GS_OP_CUT, 0) +// CHECK-NEXT:{{^}} ^ + +//============================================================================== +// expected a register name or an absolute expression + +s_setreg_b32 hwreg(HW_REG_WRONG), s2 +// CHECK: error: expected a register name or an absolute expression +// CHECK-NEXT:{{^}}s_setreg_b32 hwreg(HW_REG_WRONG), s2 +// CHECK-NEXT:{{^}} ^ + +//============================================================================== +// expected a sendmsg macro or an absolute expression + +s_sendmsg undef +// CHECK: error: expected a sendmsg macro or an absolute expression +// CHECK-NEXT:{{^}}s_sendmsg undef +// CHECK-NEXT:{{^}} ^ + +//============================================================================== +// expected a swizzle macro or an absolute expression + +ds_swizzle_b32 v8, v2 offset:SWZ(QUAD_PERM, 0, 1, 2, 3) +// CHECK: error: expected a swizzle macro or an absolute expression +// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:SWZ(QUAD_PERM, 0, 1, 2, 3) +// CHECK-NEXT:{{^}} ^ + +//============================================================================== // expected an 11-bit unsigned offset flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:4095 glc @@ -403,6 +415,22 @@ v_mov_b32_sdwa v1, sext(u) // CHECK-NEXT:{{^}} ^ //============================================================================== +// expected a hwreg macro or an absolute expression + +s_setreg_b32 undef, s2 +// CHECK: error: expected a hwreg macro or an absolute expression +// CHECK-NEXT:{{^}}s_setreg_b32 undef, s2 +// CHECK-NEXT:{{^}} ^ + +//============================================================================== +// expected an operation name or an absolute expression + +s_sendmsg sendmsg(MSG_GS, GS_OP_CUTX, 0) +// CHECK: error: expected an operation name or an absolute expression +// CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GS, GS_OP_CUTX, 0) +// CHECK-NEXT:{{^}} ^ + +//============================================================================== // failed parsing operand. image_load v[0:1], v0, s[0:7] dmask:0x9 dim:1 D diff --git a/llvm/test/MC/AMDGPU/sopk-err.s b/llvm/test/MC/AMDGPU/sopk-err.s index 2311c72..aefa479 100644 --- a/llvm/test/MC/AMDGPU/sopk-err.s +++ b/llvm/test/MC/AMDGPU/sopk-err.s @@ -14,13 +14,13 @@ s_setreg_b32 0x1f803, s2 // GCN: error: invalid immediate: only 16-bit values are legal s_setreg_b32 typo(0x40), s2 -// GCN: error: expected absolute expression +// GCN: error: expected a hwreg macro or an absolute expression s_setreg_b32 hwreg(0x40), s2 // GCN: error: invalid code of hardware register: only 6-bit values are legal s_setreg_b32 hwreg(HW_REG_WRONG), s2 -// GCN: error: expected absolute expression +// GCN: error: expected a register name or an absolute expression s_setreg_b32 hwreg(1 2,3), s2 // GCN: error: expected a comma or a closing parenthesis diff --git a/llvm/test/MC/AMDGPU/sopp-err.s b/llvm/test/MC/AMDGPU/sopp-err.s index f3181de..a8ddbe5 100644 --- a/llvm/test/MC/AMDGPU/sopp-err.s +++ b/llvm/test/MC/AMDGPU/sopp-err.s @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// s_sendmsg sendmsg(MSG_INTERRUPTX) -// GCN: error: expected absolute expression +// GCN: error: expected a message name or an absolute expression s_sendmsg sendmsg(1 -) // GCN: error: unknown token in expression @@ -26,7 +26,7 @@ s_sendmsg sendmsg(MSG_GS, GS_OP_NOP) // GCN: error: invalid operation id s_sendmsg sendmsg(MSG_GS, SYSMSG_OP_ECC_ERR_INTERRUPT) -// GCN: error: expected absolute expression +// GCN: error: expected an operation name or an absolute expression s_sendmsg sendmsg(MSG_GS, 0) // GCN: error: invalid operation id @@ -50,10 +50,10 @@ s_sendmsg sendmsg(MSG_GS, GS_OP_CUT, 0, 0) // GCN: error: expected a closing parenthesis s_sendmsg sendmsg(MSG_GSX, GS_OP_CUT, 0) -// GCN: error: expected absolute expression +// GCN: error: expected a message name or an absolute expression s_sendmsg sendmsg(MSG_GS, GS_OP_CUTX, 0) -// GCN: error: expected absolute expression +// GCN: error: expected an operation name or an absolute expression s_sendmsg sendmsg(MSG_GS, 1 -) // GCN: error: unknown token in expression -- 2.7.4