From a08fc94222d1b5be7ecbf52d4d41fa6da1d71f18 Mon Sep 17 00:00:00 2001 From: Peter Bergner Date: Thu, 27 Oct 2011 15:44:01 +0000 Subject: [PATCH] opcodes/ * ppc-opc.c (powerpc_opcodes) : Use FRT, FRA, FRB and FRBp repsectively on DFP quad instructions. --- opcodes/ChangeLog | 7 +++++++ opcodes/ppc-opc.c | 28 ++++++++++++++-------------- 2 files changed, 21 insertions(+), 14 deletions(-) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 4d18f6a..1d057a4 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,10 @@ +2011-10-27 Peter Bergner + + * ppc-opc.c (powerpc_opcodes) : Use FRT, FRA, FRB and FRBp repsectively on DFP quad + instructions. + 2011-10-26 Nick Clifton PR binutils/13348 diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 45bd08a..950a5af 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -5292,8 +5292,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"dmulq", XRC(63,34,0), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}}, {"dmulq.", XRC(63,34,1), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}}, -{"drrndq", ZRC(63,35,0), Z2_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp, RMC}}, -{"drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp, RMC}}, +{"drrndq", ZRC(63,35,0), Z2_MASK, POWER6, PPCNONE, {FRTp, FRA, FRBp, RMC}}, +{"drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, PPCNONE, {FRTp, FRA, FRBp, RMC}}, {"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCNONE, {BT}}, {"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCNONE, {BT}}, @@ -5340,27 +5340,27 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"ftsqrt", X(63,160), X_MASK|(3<<21|FRA_MASK), POWER7, PPCNONE, {BF, FRB}}, -{"dtstexq", X(63,162), X_MASK, POWER6, PPCNONE, {BF, FRAp, FRB}}, +{"dtstexq", X(63,162), X_MASK, POWER6, PPCNONE, {BF, FRAp, FRBp}}, {"dtstdcq", Z(63,194), Z_MASK, POWER6, PPCNONE, {BF, FRAp, DCM}}, {"dtstdgq", Z(63,226), Z_MASK, POWER6, PPCNONE, {BF, FRAp, DGM}}, {"drintnq", ZRC(63,227,0), Z2_MASK, POWER6, PPCNONE, {R, FRTp, FRBp, RMC}}, {"drintnq.", ZRC(63,227,1), Z2_MASK, POWER6, PPCNONE, {R, FRTp, FRBp, RMC}}, -{"dctqpq", XRC(63,258,0), X_MASK, POWER6, PPCNONE, {FRTp, FRBp}}, -{"dctqpq.", XRC(63,258,1), X_MASK, POWER6, PPCNONE, {FRTp, FRBp}}, +{"dctqpq", XRC(63,258,0), X_MASK, POWER6, PPCNONE, {FRTp, FRB}}, +{"dctqpq.", XRC(63,258,1), X_MASK, POWER6, PPCNONE, {FRTp, FRB}}, {"fabs", XRC(63,264,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}}, {"fabs.", XRC(63,264,1), XRA_MASK, COM, PPCEFS, {FRT, FRB}}, -{"dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCNONE, {FRTp, FRBp}}, -{"dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCNONE, {FRTp, FRBp}}, +{"dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCNONE, {FRT, FRBp}}, +{"dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCNONE, {FRT, FRBp}}, {"ddedpdq", XRC(63,322,0), X_MASK, POWER6, PPCNONE, {SP, FRTp, FRBp}}, {"ddedpdq.", XRC(63,322,1), X_MASK, POWER6, PPCNONE, {SP, FRTp, FRBp}}, -{"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCNONE, {FRTp, FRBp}}, -{"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCNONE, {FRTp, FRBp}}, +{"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCNONE, {FRT, FRBp}}, +{"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCNONE, {FRT, FRBp}}, {"frin", XRC(63,392,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, {"frin.", XRC(63,392,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, @@ -5382,7 +5382,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"dcmpuq", X(63,642), X_MASK, POWER6, PPCNONE, {BF, FRAp, FRBp}}, -{"dtstsfq", X(63,674), X_MASK, POWER6, PPCNONE, {BF, FRAp, FRBp}}, +{"dtstsfq", X(63,674), X_MASK, POWER6, PPCNONE, {BF, FRA, FRBp}}, {"mtfsf", XFL(63,711,0), XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}}, {"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS, {FLM, FRB}}, @@ -5392,8 +5392,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"drdpq", XRC(63,770,0), X_MASK, POWER6, PPCNONE, {FRTp, FRBp}}, {"drdpq.", XRC(63,770,1), X_MASK, POWER6, PPCNONE, {FRTp, FRBp}}, -{"dcffixq", XRC(63,802,0), X_MASK, POWER6, PPCNONE, {FRTp, FRBp}}, -{"dcffixq.", XRC(63,802,1), X_MASK, POWER6, PPCNONE, {FRTp, FRBp}}, +{"dcffixq", XRC(63,802,0), X_MASK, POWER6, PPCNONE, {FRTp, FRB}}, +{"dcffixq.", XRC(63,802,1), X_MASK, POWER6, PPCNONE, {FRTp, FRB}}, {"fctid", XRC(63,814,0), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}}, {"fctid", XRC(63,814,0), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}}, @@ -5413,8 +5413,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}}, {"fcfid.", XRC(63,846,1), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}}, -{"diexq", XRC(63,866,0), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}}, -{"diexq.", XRC(63,866,1), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}}, +{"diexq", XRC(63,866,0), X_MASK, POWER6, PPCNONE, {FRTp, FRA, FRBp}}, +{"diexq.", XRC(63,866,1), X_MASK, POWER6, PPCNONE, {FRTp, FRA, FRBp}}, {"fctidu", XRC(63,942,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}}, {"fctidu.", XRC(63,942,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}}, -- 2.7.4