From a0141c63087c11b64616d003990034d03c1cd5ef Mon Sep 17 00:00:00 2001 From: =?utf8?q?Timur=20Krist=C3=B3f?= Date: Fri, 3 Mar 2023 11:47:02 -0800 Subject: [PATCH] aco, radv: Don't use radv_shader_args in aco. MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Signed-off-by: Timur Kristóf Reviewed-by: Daniel Schürmann Part-of: --- src/amd/compiler/aco_instruction_selection.cpp | 228 ++++++++++----------- src/amd/compiler/aco_instruction_selection.h | 6 +- .../compiler/aco_instruction_selection_setup.cpp | 2 +- src/amd/compiler/aco_interface.cpp | 8 +- src/amd/compiler/aco_interface.h | 6 +- src/amd/compiler/aco_ir.h | 10 +- src/amd/vulkan/radv_shader.c | 6 +- 7 files changed, 130 insertions(+), 136 deletions(-) diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index f1c73aa..7f1ca20 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -5208,7 +5208,7 @@ wave_id_in_threadgroup(isel_context* ctx) { Builder bld(ctx->program, ctx->block); return bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), - get_arg(ctx, ctx->args->ac.merged_wave_info), Operand::c32(24u | (4u << 16))); + get_arg(ctx, ctx->args->merged_wave_info), Operand::c32(24u | (4u << 16))); } Temp @@ -5447,15 +5447,15 @@ emit_load_frag_coord(isel_context* ctx, Temp dst, unsigned num_components) aco_ptr vec(create_instruction( aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1)); for (unsigned i = 0; i < num_components; i++) { - if (ctx->args->ac.frag_pos[i].used) - vec->operands[i] = Operand(get_arg(ctx, ctx->args->ac.frag_pos[i])); + if (ctx->args->frag_pos[i].used) + vec->operands[i] = Operand(get_arg(ctx, ctx->args->frag_pos[i])); else vec->operands[i] = Operand(v1); } if (G_0286CC_POS_W_FLOAT_ENA(ctx->program->config->spi_ps_input_ena)) { assert(num_components == 4); vec->operands[3] = - bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), get_arg(ctx, ctx->args->ac.frag_pos[3])); + bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), get_arg(ctx, ctx->args->frag_pos[3])); } for (Operand& op : vec->operands) @@ -5476,9 +5476,9 @@ emit_load_frag_shading_rate(isel_context* ctx, Temp dst) /* VRS Rate X = Ancillary[2:3] * VRS Rate Y = Ancillary[4:5] */ - Temp x_rate = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1), get_arg(ctx, ctx->args->ac.ancillary), + Temp x_rate = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1), get_arg(ctx, ctx->args->ancillary), Operand::c32(2u), Operand::c32(2u)); - Temp y_rate = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1), get_arg(ctx, ctx->args->ac.ancillary), + Temp y_rate = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1), get_arg(ctx, ctx->args->ancillary), Operand::c32(4u), Operand::c32(2u)); /* xRate = xRate == 0x1 ? Horizontal2Pixels : None. */ @@ -5501,7 +5501,7 @@ visit_load_interpolated_input(isel_context* ctx, nir_intrinsic_instr* instr) Temp coords = get_ssa_temp(ctx, instr->src[0].ssa); unsigned idx = nir_intrinsic_base(instr); unsigned component = nir_intrinsic_component(instr); - Temp prim_mask = get_arg(ctx, ctx->args->ac.prim_mask); + Temp prim_mask = get_arg(ctx, ctx->args->prim_mask); assert(nir_src_is_const(instr->src[1]) && !nir_src_as_uint(instr->src[1])); @@ -5533,7 +5533,7 @@ visit_load_input(isel_context* ctx, nir_intrinsic_instr* instr) "Unimplemented non-zero nir_intrinsic_load_input offset"); Temp vertex_buffers = - convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->ac.vertex_buffers)); + convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->vertex_buffers)); unsigned location = nir_intrinsic_base(instr) - VERT_ATTRIB_GENERIC0; unsigned bitsize = instr->dest.ssa.bit_size; @@ -5561,9 +5561,9 @@ visit_load_input(isel_context* ctx, nir_intrinsic_instr* instr) Temp index; if (ctx->options->key.vs.instance_rate_inputs & (1u << location)) { uint32_t divisor = ctx->options->key.vs.instance_rate_divisors[location]; - Temp start_instance = get_arg(ctx, ctx->args->ac.start_instance); + Temp start_instance = get_arg(ctx, ctx->args->start_instance); if (divisor) { - Temp instance_id = get_arg(ctx, ctx->args->ac.instance_id); + Temp instance_id = get_arg(ctx, ctx->args->instance_id); if (divisor != 1) { Temp divided = bld.tmp(v1); emit_v_div_u32(ctx, divided, as_vgpr(ctx, instance_id), divisor); @@ -5575,8 +5575,8 @@ visit_load_input(isel_context* ctx, nir_intrinsic_instr* instr) index = bld.copy(bld.def(v1), start_instance); } } else { - index = bld.vadd32(bld.def(v1), get_arg(ctx, ctx->args->ac.base_vertex), - get_arg(ctx, ctx->args->ac.vertex_id)); + index = bld.vadd32(bld.def(v1), get_arg(ctx, ctx->args->base_vertex), + get_arg(ctx, ctx->args->vertex_id)); } Temp* const channels = (Temp*)alloca(num_channels * sizeof(Temp)); @@ -5745,7 +5745,7 @@ visit_load_input(isel_context* ctx, nir_intrinsic_instr* instr) isel_err(offset.ssa->parent_instr, "Unimplemented non-zero nir_intrinsic_load_input offset"); - Temp prim_mask = get_arg(ctx, ctx->args->ac.prim_mask); + Temp prim_mask = get_arg(ctx, ctx->args->prim_mask); unsigned idx = nir_intrinsic_base(instr); unsigned component = nir_intrinsic_component(instr); @@ -5809,8 +5809,8 @@ visit_load_tess_coord(isel_context* ctx, nir_intrinsic_instr* instr) Builder bld(ctx->program, ctx->block); Temp dst = get_ssa_temp(ctx, &instr->dest.ssa); - Operand tes_u(get_arg(ctx, ctx->args->ac.tes_u)); - Operand tes_v(get_arg(ctx, ctx->args->ac.tes_v)); + Operand tes_u(get_arg(ctx, ctx->args->tes_u)); + Operand tes_v(get_arg(ctx, ctx->args->tes_v)); Operand tes_w = Operand::zero(); if (ctx->shader->info.tess._primitive_mode == TESS_PRIMITIVE_TRIANGLES) { @@ -5880,15 +5880,15 @@ visit_load_push_constant(isel_context* ctx, nir_intrinsic_instr* instr) if (index_cv && instr->dest.ssa.bit_size >= 32) { unsigned start = (offset + index_cv->u32) / 4u; uint64_t mask = BITFIELD64_MASK(count) << start; - if ((ctx->args->ac.inline_push_const_mask | mask) == ctx->args->ac.inline_push_const_mask && - start + count <= (sizeof(ctx->args->ac.inline_push_const_mask) * 8u)) { + if ((ctx->args->inline_push_const_mask | mask) == ctx->args->inline_push_const_mask && + start + count <= (sizeof(ctx->args->inline_push_const_mask) * 8u)) { std::array elems; aco_ptr vec{create_instruction( aco_opcode::p_create_vector, Format::PSEUDO, count, 1)}; unsigned arg_index = - util_bitcount64(ctx->args->ac.inline_push_const_mask & BITFIELD64_MASK(start)); + util_bitcount64(ctx->args->inline_push_const_mask & BITFIELD64_MASK(start)); for (unsigned i = 0; i < count; ++i) { - elems[i] = get_arg(ctx, ctx->args->ac.inline_push_consts[arg_index++]); + elems[i] = get_arg(ctx, ctx->args->inline_push_consts[arg_index++]); vec->operands[i] = Operand{elems[i]}; } vec->definitions[0] = Definition(dst); @@ -5902,7 +5902,7 @@ visit_load_push_constant(isel_context* ctx, nir_intrinsic_instr* instr) if (offset != 0) // TODO check if index != 0 as well index = bld.nuw().sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand::c32(offset), index); - Temp ptr = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->ac.push_constants)); + Temp ptr = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->push_constants)); Temp vec = dst; bool trim = false; bool aligned = true; @@ -8151,12 +8151,12 @@ get_interp_param(isel_context* ctx, nir_intrinsic_op intrin, if (intrin == nir_intrinsic_load_barycentric_pixel || intrin == nir_intrinsic_load_barycentric_at_sample || intrin == nir_intrinsic_load_barycentric_at_offset) { - return get_arg(ctx, linear ? ctx->args->ac.linear_center : ctx->args->ac.persp_center); + return get_arg(ctx, linear ? ctx->args->linear_center : ctx->args->persp_center); } else if (intrin == nir_intrinsic_load_barycentric_centroid) { return linear ? ctx->linear_centroid : ctx->persp_centroid; } else { assert(intrin == nir_intrinsic_load_barycentric_sample); - return get_arg(ctx, linear ? ctx->args->ac.linear_sample : ctx->args->ac.persp_sample); + return get_arg(ctx, linear ? ctx->args->linear_sample : ctx->args->persp_sample); } } @@ -8195,7 +8195,7 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) break; } case nir_intrinsic_load_barycentric_model: { - Temp model = get_arg(ctx, ctx->args->ac.pull_model); + Temp model = get_arg(ctx, ctx->args->pull_model); assert(model.size() == 3); Temp dst = get_ssa_temp(ctx, &instr->dest.ssa); bld.copy(Definition(dst), model); @@ -8213,12 +8213,12 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) } case nir_intrinsic_load_front_face: { bld.vopc(aco_opcode::v_cmp_lg_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), - Operand::zero(), get_arg(ctx, ctx->args->ac.front_face)); + Operand::zero(), get_arg(ctx, ctx->args->front_face)); break; } case nir_intrinsic_load_view_index: { Temp dst = get_ssa_temp(ctx, &instr->dest.ssa); - bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.view_index))); + bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->view_index))); break; } case nir_intrinsic_load_frag_coord: { @@ -8229,8 +8229,8 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) emit_load_frag_shading_rate(ctx, get_ssa_temp(ctx, &instr->dest.ssa)); break; case nir_intrinsic_load_sample_pos: { - Temp posx = get_arg(ctx, ctx->args->ac.frag_pos[0]); - Temp posy = get_arg(ctx, ctx->args->ac.frag_pos[1]); + Temp posx = get_arg(ctx, ctx->args->frag_pos[0]); + Temp posy = get_arg(ctx, ctx->args->frag_pos[1]); bld.pseudo( aco_opcode::p_create_vector, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), posx.id() ? bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), posx) : Operand::zero(), @@ -8318,9 +8318,9 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) case nir_intrinsic_load_num_workgroups: { Temp dst = get_ssa_temp(ctx, &instr->dest.ssa); if (ctx->options->load_grid_size_from_user_sgpr) { - bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.num_work_groups)); + bld.copy(Definition(dst), get_arg(ctx, ctx->args->num_work_groups)); } else { - Temp addr = get_arg(ctx, ctx->args->ac.num_work_groups); + Temp addr = get_arg(ctx, ctx->args->num_work_groups); assert(addr.regClass() == s2); bld.pseudo(aco_opcode::p_create_vector, Definition(dst), bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), addr, Operand::zero()), @@ -8331,7 +8331,7 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) } case nir_intrinsic_load_ray_launch_size_addr_amd: { Temp dst = get_ssa_temp(ctx, &instr->dest.ssa); - Temp addr = get_arg(ctx, ctx->args->ac.ray_launch_size_addr); + Temp addr = get_arg(ctx, ctx->args->ray_launch_size_addr); assert(addr.regClass() == s2); bld.copy(Definition(dst), Operand(addr)); break; @@ -8344,14 +8344,14 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) /* Thread IDs are packed in VGPR0, 10 bits per component. */ for (uint32_t i = 0; i < 3; i++) { local_ids[i] = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1), - get_arg(ctx, ctx->args->ac.local_invocation_ids), + get_arg(ctx, ctx->args->local_invocation_ids), Operand::c32(i * 10u), Operand::c32(10u)); } bld.pseudo(aco_opcode::p_create_vector, Definition(dst), local_ids[0], local_ids[1], local_ids[2]); } else { - bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.local_invocation_ids))); + bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->local_invocation_ids))); } emit_split_vector(ctx, dst, 3); break; @@ -8359,7 +8359,7 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) case nir_intrinsic_load_workgroup_id: { Temp dst = get_ssa_temp(ctx, &instr->dest.ssa); if (ctx->stage.hw == HWStage::CS) { - const struct ac_arg* ids = ctx->args->ac.workgroup_ids; + const struct ac_arg* ids = ctx->args->workgroup_ids; bld.pseudo(aco_opcode::p_create_vector, Definition(dst), ids[0].used ? Operand(get_arg(ctx, ids[0])) : Operand::zero(), ids[1].used ? Operand(get_arg(ctx, ids[1])) : Operand::zero(), @@ -8376,14 +8376,14 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) /* On GFX11, RelAutoIndex is WaveID * WaveSize + ThreadID. */ Temp wave_id = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), - get_arg(ctx, ctx->args->ac.tcs_wave_id), Operand::c32(0u | (3u << 16))); + get_arg(ctx, ctx->args->tcs_wave_id), Operand::c32(0u | (3u << 16))); Temp temp = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), wave_id, Operand::c32(ctx->program->wave_size)); emit_mbcnt(ctx, get_ssa_temp(ctx, &instr->dest.ssa), Operand(), Operand(temp)); } else { bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), - get_arg(ctx, ctx->args->ac.vs_rel_patch_id)); + get_arg(ctx, ctx->args->vs_rel_patch_id)); } break; } else if (ctx->stage.hw == HWStage::GS || ctx->stage.hw == HWStage::NGG) { @@ -8403,14 +8403,14 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just * feed that to v_or */ Temp tg_num = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), - Operand::c32(0xfc0u), get_arg(ctx, ctx->args->ac.tg_size)); + Operand::c32(0xfc0u), get_arg(ctx, ctx->args->tg_size)); bld.vop2(aco_opcode::v_or_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), tg_num, id); } else { /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */ Temp tg_num = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), - get_arg(ctx, ctx->args->ac.tg_size), Operand::c32(0x6u | (0x6u << 16))); + get_arg(ctx, ctx->args->tg_size), Operand::c32(0x6u | (0x6u << 16))); bld.vop3(aco_opcode::v_lshl_or_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), tg_num, Operand::c32(0x5u), id); } @@ -8419,12 +8419,12 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) case nir_intrinsic_load_subgroup_id: { if (ctx->stage.hw == HWStage::CS) { bld.sop2(aco_opcode::s_bfe_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), - bld.def(s1, scc), get_arg(ctx, ctx->args->ac.tg_size), + bld.def(s1, scc), get_arg(ctx, ctx->args->tg_size), Operand::c32(0x6u | (0x6u << 16))); } else if (ctx->stage.hw == HWStage::NGG) { /* Get the id of the current wave within the threadgroup (workgroup) */ bld.sop2(aco_opcode::s_bfe_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), - bld.def(s1, scc), get_arg(ctx, ctx->args->ac.merged_wave_info), + bld.def(s1, scc), get_arg(ctx, ctx->args->merged_wave_info), Operand::c32(24u | (4u << 16))); } else { bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), Operand::zero()); @@ -8438,10 +8438,10 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) case nir_intrinsic_load_num_subgroups: { if (ctx->stage.hw == HWStage::CS) bld.sop2(aco_opcode::s_and_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), - bld.def(s1, scc), Operand::c32(0x3fu), get_arg(ctx, ctx->args->ac.tg_size)); + bld.def(s1, scc), Operand::c32(0x3fu), get_arg(ctx, ctx->args->tg_size)); else if (ctx->stage.hw == HWStage::NGG) bld.sop2(aco_opcode::s_bfe_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), - bld.def(s1, scc), get_arg(ctx, ctx->args->ac.merged_wave_info), + bld.def(s1, scc), get_arg(ctx, ctx->args->merged_wave_info), Operand::c32(28u | (4u << 16))); else bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), Operand::c32(0x1u)); @@ -8530,7 +8530,7 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) } case nir_intrinsic_load_sample_id: { bld.vop3(aco_opcode::v_bfe_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), - get_arg(ctx, ctx->args->ac.ancillary), Operand::c32(8u), Operand::c32(4u)); + get_arg(ctx, ctx->args->ancillary), Operand::c32(8u), Operand::c32(4u)); break; } case nir_intrinsic_read_first_invocation: { @@ -8941,27 +8941,27 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) } case nir_intrinsic_load_vertex_id_zero_base: { Temp dst = get_ssa_temp(ctx, &instr->dest.ssa); - bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.vertex_id)); + bld.copy(Definition(dst), get_arg(ctx, ctx->args->vertex_id)); break; } case nir_intrinsic_load_first_vertex: { Temp dst = get_ssa_temp(ctx, &instr->dest.ssa); - bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.base_vertex)); + bld.copy(Definition(dst), get_arg(ctx, ctx->args->base_vertex)); break; } case nir_intrinsic_load_base_instance: { Temp dst = get_ssa_temp(ctx, &instr->dest.ssa); - bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.start_instance)); + bld.copy(Definition(dst), get_arg(ctx, ctx->args->start_instance)); break; } case nir_intrinsic_load_instance_id: { Temp dst = get_ssa_temp(ctx, &instr->dest.ssa); - bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.instance_id)); + bld.copy(Definition(dst), get_arg(ctx, ctx->args->instance_id)); break; } case nir_intrinsic_load_draw_id: { Temp dst = get_ssa_temp(ctx, &instr->dest.ssa); - bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.draw_id)); + bld.copy(Definition(dst), get_arg(ctx, ctx->args->draw_id)); break; } case nir_intrinsic_load_invocation_id: { @@ -8970,11 +8970,11 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) if (ctx->shader->info.stage == MESA_SHADER_GEOMETRY) { if (ctx->options->gfx_level >= GFX10) bld.vop2_e64(aco_opcode::v_and_b32, Definition(dst), Operand::c32(127u), - get_arg(ctx, ctx->args->ac.gs_invocation_id)); + get_arg(ctx, ctx->args->gs_invocation_id)); else - bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.gs_invocation_id)); + bld.copy(Definition(dst), get_arg(ctx, ctx->args->gs_invocation_id)); } else if (ctx->shader->info.stage == MESA_SHADER_TESS_CTRL) { - bld.vop3(aco_opcode::v_bfe_u32, Definition(dst), get_arg(ctx, ctx->args->ac.tcs_rel_ids), + bld.vop3(aco_opcode::v_bfe_u32, Definition(dst), get_arg(ctx, ctx->args->tcs_rel_ids), Operand::c32(8u), Operand::c32(5u)); } else { unreachable("Unsupported stage for load_invocation_id"); @@ -8987,22 +8987,22 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) switch (ctx->shader->info.stage) { case MESA_SHADER_GEOMETRY: - bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.gs_prim_id)); + bld.copy(Definition(dst), get_arg(ctx, ctx->args->gs_prim_id)); break; case MESA_SHADER_TESS_CTRL: - bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.tcs_patch_id)); + bld.copy(Definition(dst), get_arg(ctx, ctx->args->tcs_patch_id)); break; case MESA_SHADER_TESS_EVAL: - bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.tes_patch_id)); + bld.copy(Definition(dst), get_arg(ctx, ctx->args->tes_patch_id)); break; default: if (ctx->stage.hw == HWStage::NGG && !ctx->stage.has(SWStage::GS)) { /* In case of NGG, the GS threads always have the primitive ID * even if there is no SW GS. */ - bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.gs_prim_id)); + bld.copy(Definition(dst), get_arg(ctx, ctx->args->gs_prim_id)); break; } else if (ctx->shader->info.stage == MESA_SHADER_VERTEX) { - bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.vs_prim_id)); + bld.copy(Definition(dst), get_arg(ctx, ctx->args->vs_prim_id)); break; } unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id"); @@ -9047,7 +9047,7 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) } case nir_intrinsic_load_sbt_base_amd: { Temp dst = get_ssa_temp(ctx, &instr->dest.ssa); - Temp addr = get_arg(ctx, ctx->args->ac.sbt_descriptors); + Temp addr = get_arg(ctx, ctx->args->sbt_descriptors); assert(addr.regClass() == s2); bld.copy(Definition(dst), Operand(addr)); break; @@ -9055,25 +9055,25 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) case nir_intrinsic_bvh64_intersect_ray_amd: visit_bvh64_intersect_ray_amd(ctx, instr); break; case nir_intrinsic_load_rt_dynamic_callable_stack_base_amd: bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), - get_arg(ctx, ctx->args->ac.rt_dynamic_callable_stack_base)); + get_arg(ctx, ctx->args->rt_dynamic_callable_stack_base)); ctx->program->rt_stack = true; break; case nir_intrinsic_overwrite_vs_arguments_amd: { - ctx->arg_temps[ctx->args->ac.vertex_id.arg_index] = get_ssa_temp(ctx, instr->src[0].ssa); - ctx->arg_temps[ctx->args->ac.instance_id.arg_index] = get_ssa_temp(ctx, instr->src[1].ssa); + ctx->arg_temps[ctx->args->vertex_id.arg_index] = get_ssa_temp(ctx, instr->src[0].ssa); + ctx->arg_temps[ctx->args->instance_id.arg_index] = get_ssa_temp(ctx, instr->src[1].ssa); break; } case nir_intrinsic_overwrite_tes_arguments_amd: { - ctx->arg_temps[ctx->args->ac.tes_u.arg_index] = get_ssa_temp(ctx, instr->src[0].ssa); - ctx->arg_temps[ctx->args->ac.tes_v.arg_index] = get_ssa_temp(ctx, instr->src[1].ssa); - ctx->arg_temps[ctx->args->ac.tes_rel_patch_id.arg_index] = + ctx->arg_temps[ctx->args->tes_u.arg_index] = get_ssa_temp(ctx, instr->src[0].ssa); + ctx->arg_temps[ctx->args->tes_v.arg_index] = get_ssa_temp(ctx, instr->src[1].ssa); + ctx->arg_temps[ctx->args->tes_rel_patch_id.arg_index] = get_ssa_temp(ctx, instr->src[3].ssa); - ctx->arg_temps[ctx->args->ac.tes_patch_id.arg_index] = get_ssa_temp(ctx, instr->src[2].ssa); + ctx->arg_temps[ctx->args->tes_patch_id.arg_index] = get_ssa_temp(ctx, instr->src[2].ssa); break; } case nir_intrinsic_load_scalar_arg_amd: case nir_intrinsic_load_vector_arg_amd: { - assert(nir_intrinsic_base(instr) < ctx->args->ac.arg_count); + assert(nir_intrinsic_base(instr) < ctx->args->arg_count); Temp dst = get_ssa_temp(ctx, &instr->dest.ssa); Temp src = ctx->arg_temps[nir_intrinsic_base(instr)]; assert(src.id()); @@ -11240,12 +11240,12 @@ Pseudo_instruction* add_startpgm(struct isel_context* ctx) { unsigned def_count = 0; - for (unsigned i = 0; i < ctx->args->ac.arg_count; i++) { - if (ctx->args->ac.args[i].skip) + for (unsigned i = 0; i < ctx->args->arg_count; i++) { + if (ctx->args->args[i].skip) continue; - unsigned align = MIN2(4, util_next_power_of_two(ctx->args->ac.args[i].size)); - if (ctx->args->ac.args[i].file == AC_ARG_SGPR && ctx->args->ac.args[i].offset % align) - def_count += ctx->args->ac.args[i].size; + unsigned align = MIN2(4, util_next_power_of_two(ctx->args->args[i].size)); + if (ctx->args->args[i].file == AC_ARG_SGPR && ctx->args->args[i].offset % align) + def_count += ctx->args->args[i].size; else def_count++; } @@ -11253,13 +11253,13 @@ add_startpgm(struct isel_context* ctx) Pseudo_instruction* startpgm = create_instruction(aco_opcode::p_startpgm, Format::PSEUDO, 0, def_count); ctx->block->instructions.emplace_back(startpgm); - for (unsigned i = 0, arg = 0; i < ctx->args->ac.arg_count; i++) { - if (ctx->args->ac.args[i].skip) + for (unsigned i = 0, arg = 0; i < ctx->args->arg_count; i++) { + if (ctx->args->args[i].skip) continue; - enum ac_arg_regfile file = ctx->args->ac.args[i].file; - unsigned size = ctx->args->ac.args[i].size; - unsigned reg = ctx->args->ac.args[i].offset; + enum ac_arg_regfile file = ctx->args->args[i].file; + unsigned size = ctx->args->args[i].size; + unsigned reg = ctx->args->args[i].offset; RegClass type = RegClass(file == AC_ARG_SGPR ? RegType::sgpr : RegType::vgpr, size); if (file == AC_ARG_SGPR && reg % MIN2(4, util_next_power_of_two(size))) { @@ -11276,7 +11276,7 @@ add_startpgm(struct isel_context* ctx) ctx->arg_temps[i] = dst; startpgm->definitions[arg++] = def; - if (ctx->args->ac.args[i].pending_vmem) { + if (ctx->args->args[i].pending_vmem) { assert(file == AC_ARG_VGPR); ctx->program->args_pending_vmem.push_back(def); } @@ -11286,9 +11286,9 @@ add_startpgm(struct isel_context* ctx) /* Stash these in the program so that they can be accessed later when * handling spilling. */ - ctx->program->private_segment_buffer = get_arg(ctx, ctx->args->ac.ring_offsets); + ctx->program->private_segment_buffer = get_arg(ctx, ctx->args->ring_offsets); if (ctx->program->gfx_level <= GFX10_3) { - ctx->program->scratch_offset = get_arg(ctx, ctx->args->ac.scratch_offset); + ctx->program->scratch_offset = get_arg(ctx, ctx->args->scratch_offset); if (ctx->program->gfx_level >= GFX9) { Operand scratch_offset(ctx->program->scratch_offset); @@ -11309,25 +11309,25 @@ fix_ls_vgpr_init_bug(isel_context* ctx, Pseudo_instruction* startpgm) Builder bld(ctx->program, ctx->block); constexpr unsigned hs_idx = 1u; Builder::Result hs_thread_count = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), - get_arg(ctx, ctx->args->ac.merged_wave_info), + get_arg(ctx, ctx->args->merged_wave_info), Operand::c32((8u << 16) | (hs_idx * 8u))); Temp ls_has_nonzero_hs_threads = bool_to_vector_condition(ctx, hs_thread_count.def(1).getTemp()); /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */ Temp instance_id = - bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), get_arg(ctx, ctx->args->ac.vertex_id), - get_arg(ctx, ctx->args->ac.instance_id), ls_has_nonzero_hs_threads); + bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), get_arg(ctx, ctx->args->vertex_id), + get_arg(ctx, ctx->args->instance_id), ls_has_nonzero_hs_threads); Temp vs_rel_patch_id = - bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), get_arg(ctx, ctx->args->ac.tcs_rel_ids), - get_arg(ctx, ctx->args->ac.vs_rel_patch_id), ls_has_nonzero_hs_threads); + bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), get_arg(ctx, ctx->args->tcs_rel_ids), + get_arg(ctx, ctx->args->vs_rel_patch_id), ls_has_nonzero_hs_threads); Temp vertex_id = - bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), get_arg(ctx, ctx->args->ac.tcs_patch_id), - get_arg(ctx, ctx->args->ac.vertex_id), ls_has_nonzero_hs_threads); + bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), get_arg(ctx, ctx->args->tcs_patch_id), + get_arg(ctx, ctx->args->vertex_id), ls_has_nonzero_hs_threads); - ctx->arg_temps[ctx->args->ac.instance_id.arg_index] = instance_id; - ctx->arg_temps[ctx->args->ac.vs_rel_patch_id.arg_index] = vs_rel_patch_id; - ctx->arg_temps[ctx->args->ac.vertex_id.arg_index] = vertex_id; + ctx->arg_temps[ctx->args->instance_id.arg_index] = instance_id; + ctx->arg_temps[ctx->args->vs_rel_patch_id.arg_index] = vs_rel_patch_id; + ctx->arg_temps[ctx->args->vertex_id.arg_index] = vertex_id; } void @@ -11356,21 +11356,21 @@ handle_bc_optimize(isel_context* ctx) bool uses_linear_centroid = G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena); if (uses_persp_centroid) - ctx->persp_centroid = get_arg(ctx, ctx->args->ac.persp_centroid); + ctx->persp_centroid = get_arg(ctx, ctx->args->persp_centroid); if (uses_linear_centroid) - ctx->linear_centroid = get_arg(ctx, ctx->args->ac.linear_centroid); + ctx->linear_centroid = get_arg(ctx, ctx->args->linear_centroid); if (uses_center && (uses_persp_centroid || uses_linear_centroid)) { Temp sel = bld.vopc_e64(aco_opcode::v_cmp_lt_i32, bld.def(bld.lm), - get_arg(ctx, ctx->args->ac.prim_mask), Operand::zero()); + get_arg(ctx, ctx->args->prim_mask), Operand::zero()); if (uses_persp_centroid) { Temp new_coord[2]; for (unsigned i = 0; i < 2; i++) { Temp persp_centroid = - emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.persp_centroid), i, v1); + emit_extract_vector(ctx, get_arg(ctx, ctx->args->persp_centroid), i, v1); Temp persp_center = - emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.persp_center), i, v1); + emit_extract_vector(ctx, get_arg(ctx, ctx->args->persp_center), i, v1); new_coord[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), persp_centroid, persp_center, sel); } @@ -11384,9 +11384,9 @@ handle_bc_optimize(isel_context* ctx) Temp new_coord[2]; for (unsigned i = 0; i < 2; i++) { Temp linear_centroid = - emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.linear_centroid), i, v1); + emit_extract_vector(ctx, get_arg(ctx, ctx->args->linear_centroid), i, v1); Temp linear_center = - emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.linear_center), i, v1); + emit_extract_vector(ctx, get_arg(ctx, ctx->args->linear_center), i, v1); new_coord[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), linear_centroid, linear_center, sel); } @@ -11496,9 +11496,9 @@ merged_wave_info_to_mask(isel_context* ctx, unsigned i) /* lanecount_to_mask() only cares about s0.u[6:0] so we don't need either s_bfe nor s_and here */ Temp count = i == 0 - ? get_arg(ctx, ctx->args->ac.merged_wave_info) + ? get_arg(ctx, ctx->args->merged_wave_info) : bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), - get_arg(ctx, ctx->args->ac.merged_wave_info), Operand::c32(i * 8u)); + get_arg(ctx, ctx->args->merged_wave_info), Operand::c32(i * 8u)); return lanecount_to_mask(ctx, count); } @@ -11573,7 +11573,7 @@ void select_program(Program* program, unsigned shader_count, struct nir_shader* const* shaders, ac_shader_config* config, const struct aco_compiler_options* options, const struct aco_shader_info* info, - const struct radv_shader_args* args) + const struct ac_shader_args* args) { isel_context ctx = setup_isel_context(program, shader_count, shaders, config, options, info, args, false); if_context ic_merged_wave_info; @@ -11646,11 +11646,11 @@ select_program(Program* program, unsigned shader_count, struct nir_shader* const if (ctx.stage == vertex_geometry_gs || ctx.stage == tess_eval_geometry_gs) { ctx.gs_wave_id = bld.pseudo(aco_opcode::p_extract, bld.def(s1, m0), bld.def(s1, scc), - get_arg(&ctx, args->ac.merged_wave_info), Operand::c32(2u), + get_arg(&ctx, args->merged_wave_info), Operand::c32(2u), Operand::c32(8u), Operand::zero()); } } else if (ctx.stage == geometry_gs) - ctx.gs_wave_id = get_arg(&ctx, args->ac.gs_wave_id); + ctx.gs_wave_id = get_arg(&ctx, args->gs_wave_id); if (ctx.stage == fragment_fs) handle_bc_optimize(&ctx); @@ -11697,7 +11697,7 @@ void select_trap_handler_shader(Program* program, struct nir_shader* shader, ac_shader_config* config, const struct aco_compiler_options* options, const struct aco_shader_info* info, - const struct radv_shader_args* args) + const struct ac_shader_args* args) { assert(options->gfx_level == GFX8); @@ -11755,13 +11755,13 @@ select_trap_handler_shader(Program* program, struct nir_shader* shader, ac_shade } Operand -get_arg_fixed(const struct radv_shader_args* args, struct ac_arg arg) +get_arg_fixed(const struct ac_shader_args* args, struct ac_arg arg) { assert(arg.used); - enum ac_arg_regfile file = args->ac.args[arg.arg_index].file; - unsigned size = args->ac.args[arg.arg_index].size; - unsigned reg = args->ac.args[arg.arg_index].offset; + enum ac_arg_regfile file = args->args[arg.arg_index].file; + unsigned size = args->args[arg.arg_index].size; + unsigned reg = args->args[arg.arg_index].offset; return Operand(PhysReg(file == AC_ARG_SGPR ? reg : reg + 256), RegClass(file == AC_ARG_SGPR ? RegType::sgpr : RegType::vgpr, size)); @@ -11797,7 +11797,7 @@ load_vb_descs(Builder& bld, PhysReg dest, Operand base, unsigned start, unsigned } Operand -calc_nontrivial_instance_id(Builder& bld, const struct radv_shader_args* args, +calc_nontrivial_instance_id(Builder& bld, const struct ac_shader_args* args, const struct aco_vs_prolog_info* pinfo, unsigned index, Operand instance_id, Operand start_instance, PhysReg tmp_sgpr, PhysReg tmp_vgpr0, PhysReg tmp_vgpr1) @@ -11861,7 +11861,7 @@ calc_nontrivial_instance_id(Builder& bld, const struct radv_shader_args* args, void select_vs_prolog(Program* program, const struct aco_vs_prolog_info* pinfo, ac_shader_config* config, const struct aco_compiler_options* options, const struct aco_shader_info* info, - const struct radv_shader_args* args, unsigned* num_preserved_sgprs) + const struct ac_shader_args* args, unsigned* num_preserved_sgprs) { assert(pinfo->num_attributes > 0); @@ -11897,10 +11897,10 @@ select_vs_prolog(Program* program, const struct aco_vs_prolog_info* pinfo, ac_sh PhysReg desc( align((has_nontrivial_divisors ? prolog_input : vertex_buffers).advance(8).reg(), 4)); - Operand start_instance = get_arg_fixed(args, args->ac.start_instance); - Operand instance_id = get_arg_fixed(args, args->ac.instance_id); + Operand start_instance = get_arg_fixed(args, args->start_instance); + Operand instance_id = get_arg_fixed(args, args->instance_id); - PhysReg attributes_start(256 + args->ac.num_vgprs_used); + PhysReg attributes_start(256 + args->num_vgprs_used); /* choose vgprs that won't be used for anything else until the last attribute load */ PhysReg vertex_index(attributes_start.reg() + pinfo->num_attributes * 4 - 1); PhysReg instance_index(attributes_start.reg() + pinfo->num_attributes * 4 - 2); @@ -11909,7 +11909,7 @@ select_vs_prolog(Program* program, const struct aco_vs_prolog_info* pinfo, ac_sh PhysReg nontrivial_tmp_vgpr1(attributes_start.reg() + pinfo->num_attributes * 4); bld.sop1(aco_opcode::s_mov_b32, Definition(vertex_buffers, s1), - get_arg_fixed(args, args->ac.vertex_buffers)); + get_arg_fixed(args, args->vertex_buffers)); if (options->address32_hi >= 0xffff8000 || options->address32_hi <= 0x7fff) { bld.sopk(aco_opcode::s_movk_i32, Definition(vertex_buffers.advance(4), s1), options->address32_hi & 0xFFFF); @@ -11936,7 +11936,7 @@ select_vs_prolog(Program* program, const struct aco_vs_prolog_info* pinfo, ac_sh if (loc == 0) { /* perform setup while we load the descriptors */ if (pinfo->is_ngg || pinfo->next_stage != MESA_SHADER_VERTEX) { - Operand count = get_arg_fixed(args, args->ac.merged_wave_info); + Operand count = get_arg_fixed(args, args->merged_wave_info); bld.sop2(aco_opcode::s_bfm_b64, Definition(exec, s2), count, Operand::c32(0u)); if (program->wave_size == 64) { bld.sopc(aco_opcode::s_bitcmp1_b32, Definition(scc, s1), count, @@ -11954,8 +11954,8 @@ select_vs_prolog(Program* program, const struct aco_vs_prolog_info* pinfo, ac_sh } bool needs_vertex_index = ~pinfo->state.instance_rate_inputs & attrib_mask; if (needs_vertex_index) - bld.vadd32(Definition(vertex_index, v1), get_arg_fixed(args, args->ac.base_vertex), - get_arg_fixed(args, args->ac.vertex_id), false, Operand(s2), true); + bld.vadd32(Definition(vertex_index, v1), get_arg_fixed(args, args->base_vertex), + get_arg_fixed(args, args->vertex_id), false, Operand(s2), true); if (needs_instance_index) bld.vadd32(Definition(instance_index, v1), start_instance, instance_id, false, Operand(s2), true); @@ -12104,7 +12104,7 @@ select_vs_prolog(Program* program, const struct aco_vs_prolog_info* pinfo, ac_sh void select_ps_epilog(Program* program, const struct aco_ps_epilog_info* einfo, ac_shader_config* config, const struct aco_compiler_options* options, const struct aco_shader_info* info, - const struct radv_shader_args* args) + const struct ac_shader_args* args) { isel_context ctx = setup_isel_context(program, 0, NULL, config, options, info, args, true); diff --git a/src/amd/compiler/aco_instruction_selection.h b/src/amd/compiler/aco_instruction_selection.h index bc2ff89..31bb55b 100644 --- a/src/amd/compiler/aco_instruction_selection.h +++ b/src/amd/compiler/aco_instruction_selection.h @@ -27,8 +27,6 @@ #include "aco_ir.h" -#include "vulkan/radv_shader_args.h" - #include #include #include @@ -55,7 +53,7 @@ struct shader_io_state { struct isel_context { const struct aco_compiler_options* options; - const struct radv_shader_args* args; + const struct ac_shader_args* args; Program* program; nir_shader* shader; uint32_t constant_data_offset; @@ -128,7 +126,7 @@ isel_context setup_isel_context(Program* program, unsigned shader_count, struct nir_shader* const* shaders, ac_shader_config* config, const struct aco_compiler_options* options, const struct aco_shader_info* info, - const struct radv_shader_args* args, bool is_ps_epilog); + const struct ac_shader_args* args, bool is_ps_epilog); } // namespace aco diff --git a/src/amd/compiler/aco_instruction_selection_setup.cpp b/src/amd/compiler/aco_instruction_selection_setup.cpp index dfb53de..df59b63 100644 --- a/src/amd/compiler/aco_instruction_selection_setup.cpp +++ b/src/amd/compiler/aco_instruction_selection_setup.cpp @@ -803,7 +803,7 @@ isel_context setup_isel_context(Program* program, unsigned shader_count, struct nir_shader* const* shaders, ac_shader_config* config, const struct aco_compiler_options* options, const struct aco_shader_info* info, - const struct radv_shader_args* args, bool is_ps_epilog) + const struct ac_shader_args* args, bool is_ps_epilog) { SWStage sw_stage = SWStage::None; for (unsigned i = 0; i < shader_count; i++) { diff --git a/src/amd/compiler/aco_interface.cpp b/src/amd/compiler/aco_interface.cpp index f5bce75..0664d64 100644 --- a/src/amd/compiler/aco_interface.cpp +++ b/src/amd/compiler/aco_interface.cpp @@ -26,8 +26,6 @@ #include "aco_ir.h" -#include "vulkan/radv_shader_args.h" - #include "util/memstream.h" #include @@ -213,7 +211,7 @@ void aco_compile_shader(const struct aco_compiler_options* options, const struct aco_shader_info* info, unsigned shader_count, struct nir_shader* const* shaders, - const struct radv_shader_args *args, + const struct ac_shader_args *args, aco_callback *build_binary, void **binary) { @@ -271,7 +269,7 @@ aco_compile_shader(const struct aco_compiler_options* options, void aco_compile_vs_prolog(const struct aco_compiler_options* options, const struct aco_shader_info* info, const struct aco_vs_prolog_info* pinfo, - const struct radv_shader_args* args, aco_shader_part_callback* build_prolog, + const struct ac_shader_args* args, aco_shader_part_callback* build_prolog, void** binary) { aco::init(); @@ -315,7 +313,7 @@ aco_compile_vs_prolog(const struct aco_compiler_options* options, void aco_compile_ps_epilog(const struct aco_compiler_options* options, const struct aco_shader_info* info, const struct aco_ps_epilog_info* pinfo, - const struct radv_shader_args* args, aco_shader_part_callback* build_epilog, + const struct ac_shader_args* args, aco_shader_part_callback* build_epilog, void** binary) { aco::init(); diff --git a/src/amd/compiler/aco_interface.h b/src/amd/compiler/aco_interface.h index ed91fdf..5f4c378 100644 --- a/src/amd/compiler/aco_interface.h +++ b/src/amd/compiler/aco_interface.h @@ -71,20 +71,20 @@ extern const struct aco_compiler_statistic_info* aco_statistic_infos; void aco_compile_shader(const struct aco_compiler_options* options, const struct aco_shader_info* info, unsigned shader_count, struct nir_shader* const* shaders, - const struct radv_shader_args *args, + const struct ac_shader_args *args, aco_callback *build_binary, void **binary); void aco_compile_vs_prolog(const struct aco_compiler_options* options, const struct aco_shader_info* info, const struct aco_vs_prolog_info* prolog_info, - const struct radv_shader_args* args, + const struct ac_shader_args* args, aco_shader_part_callback* build_prolog, void** binary); void aco_compile_ps_epilog(const struct aco_compiler_options* options, const struct aco_shader_info* info, const struct aco_ps_epilog_info* epilog_info, - const struct radv_shader_args* args, + const struct ac_shader_args* args, aco_shader_part_callback* build_epilog, void** binary); uint64_t aco_get_codegen_flags(); diff --git a/src/amd/compiler/aco_ir.h b/src/amd/compiler/aco_ir.h index 2fc8579..a44eafd 100644 --- a/src/amd/compiler/aco_ir.h +++ b/src/amd/compiler/aco_ir.h @@ -38,8 +38,6 @@ #include #include -struct radv_shader_args; - namespace aco { extern uint64_t debug_flags; @@ -2192,20 +2190,20 @@ void init_program(Program* program, Stage stage, const struct aco_shader_info* i void select_program(Program* program, unsigned shader_count, struct nir_shader* const* shaders, ac_shader_config* config, const struct aco_compiler_options* options, const struct aco_shader_info* info, - const struct radv_shader_args* args); + const struct ac_shader_args* args); void select_trap_handler_shader(Program* program, struct nir_shader* shader, ac_shader_config* config, const struct aco_compiler_options* options, const struct aco_shader_info* info, - const struct radv_shader_args* args); + const struct ac_shader_args* args); void select_vs_prolog(Program* program, const struct aco_vs_prolog_info* pinfo, ac_shader_config* config, const struct aco_compiler_options* options, - const struct aco_shader_info* info, const struct radv_shader_args* args, + const struct aco_shader_info* info, const struct ac_shader_args* args, unsigned* num_preserved_sgprs); void select_ps_epilog(Program* program, const struct aco_ps_epilog_info* epilog_info, ac_shader_config* config, const struct aco_compiler_options* options, - const struct aco_shader_info* info, const struct radv_shader_args* args); + const struct aco_shader_info* info, const struct ac_shader_args* args); void lower_phis(Program* program); void calc_min_waves(Program* program); diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index de5779c..4436bf2 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -2389,7 +2389,7 @@ shader_compile(struct radv_device *device, struct nir_shader *const *shaders, in struct aco_compiler_options ac_opts; radv_aco_convert_opts(&ac_opts, &options, args); radv_aco_convert_shader_info(&ac_info, info, args); - aco_compile_shader(&ac_opts, &ac_info, shader_count, shaders, args, &radv_aco_build_shader_binary, (void **)&binary); + aco_compile_shader(&ac_opts, &ac_info, shader_count, shaders, &args->ac, &radv_aco_build_shader_binary, (void **)&binary); } binary->info = *info; @@ -2545,7 +2545,7 @@ radv_create_vs_prolog(struct radv_device *device, const struct radv_vs_prolog_ke radv_aco_convert_shader_info(&ac_info, &info, &args); radv_aco_convert_opts(&ac_opts, &options, &args); radv_aco_convert_vs_prolog_key(&ac_prolog_info, key, &args); - aco_compile_vs_prolog(&ac_opts, &ac_info, &ac_prolog_info, &args, &radv_aco_build_shader_part, + aco_compile_vs_prolog(&ac_opts, &ac_info, &ac_prolog_info, &args.ac, &radv_aco_build_shader_part, (void **)&binary); prolog = radv_shader_part_create(binary, info.wave_size); @@ -2610,7 +2610,7 @@ radv_create_ps_epilog(struct radv_device *device, const struct radv_ps_epilog_ke radv_aco_convert_shader_info(&ac_info, &info, &args); radv_aco_convert_opts(&ac_opts, &options, &args); radv_aco_convert_ps_epilog_key(&ac_epilog_info, key, &args); - aco_compile_ps_epilog(&ac_opts, &ac_info, &ac_epilog_info, &args, &radv_aco_build_shader_part, + aco_compile_ps_epilog(&ac_opts, &ac_info, &ac_epilog_info, &args.ac, &radv_aco_build_shader_part, (void **)&binary); epilog = radv_shader_part_create(binary, info.wave_size); -- 2.7.4