From 9ff2380ea6d2d186471b394227e332b705f1c7c9 Mon Sep 17 00:00:00 2001 From: Hiroshi Inoue Date: Mon, 9 Apr 2018 04:37:53 +0000 Subject: [PATCH] [NFC] fix trivial typos in comments and error message "is is" -> "is", "are are" -> "are" llvm-svn: 329546 --- llvm/lib/DebugInfo/PDB/GenericError.cpp | 2 +- llvm/lib/Support/APInt.cpp | 2 +- llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp | 2 +- llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp | 2 +- llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp | 2 +- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 2 +- llvm/lib/Transforms/Scalar/NewGVN.cpp | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/llvm/lib/DebugInfo/PDB/GenericError.cpp b/llvm/lib/DebugInfo/PDB/GenericError.cpp index 4fcecb9..2a677b9 100644 --- a/llvm/lib/DebugInfo/PDB/GenericError.cpp +++ b/llvm/lib/DebugInfo/PDB/GenericError.cpp @@ -30,7 +30,7 @@ public: return "Type server PDB was not found."; case generic_error_code::dia_sdk_not_present: return "LLVM was not compiled with support for DIA. This usually means " - "that you are are not using MSVC, or your Visual Studio " + "that you are not using MSVC, or your Visual Studio " "installation " "is corrupt."; case generic_error_code::invalid_path: diff --git a/llvm/lib/Support/APInt.cpp b/llvm/lib/Support/APInt.cpp index 603648b..cc3cedd 100644 --- a/llvm/lib/Support/APInt.cpp +++ b/llvm/lib/Support/APInt.cpp @@ -922,7 +922,7 @@ void APInt::ashrSlowCase(unsigned ShiftAmt) { // Save the original sign bit for later. bool Negative = isNegative(); - // WordShift is the inter-part shift; BitShift is is intra-part shift. + // WordShift is the inter-part shift; BitShift is intra-part shift. unsigned WordShift = ShiftAmt / APINT_BITS_PER_WORD; unsigned BitShift = ShiftAmt % APINT_BITS_PER_WORD; diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index 2abe2a0..69b4654 100644 --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -4514,7 +4514,7 @@ AArch64AsmParser::classifySymbolRef(const MCExpr *Expr, BE->getOpcode() != MCBinaryExpr::Sub) return false; - // See if the addend is is a constant, otherwise there's more going + // See if the addend is a constant, otherwise there's more going // on here than we can deal with. auto AddendExpr = dyn_cast(BE->getRHS()); if (!AddendExpr) diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp index ff507ab..4fb1db5 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp @@ -239,7 +239,7 @@ const char *ARMAsmBackend::reasonForFixupRelaxation(const MCFixup &Fixup, } case ARM::fixup_arm_thumb_cb: { // If we have a Thumb CBZ or CBNZ instruction and its target is the next - // instruction it is is actually out of range for the instruction. + // instruction it is actually out of range for the instruction. // It will be changed to a NOP. int64_t Offset = (Value & ~1); if (Offset == 2) diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp index f1f35f4..0dab789 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp @@ -1520,7 +1520,7 @@ unsigned ARMMCCodeEmitter:: getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { - // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the + // 10 bits. lower 5 bits are the lsb of the mask, high five bits are the // msb of the mask. const MCOperand &MO = MI.getOperand(Op); uint32_t v = ~MO.getImm(); diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index 59654f9..521d72b 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -953,7 +953,7 @@ bool RISCVAsmParser::classifySymbolRef(const MCExpr *Expr, isa(BE->getRHS())) return true; - // See if the addend is is a constant, otherwise there's more going + // See if the addend is a constant, otherwise there's more going // on here than we can deal with. auto AddendExpr = dyn_cast(BE->getRHS()); if (!AddendExpr) diff --git a/llvm/lib/Transforms/Scalar/NewGVN.cpp b/llvm/lib/Transforms/Scalar/NewGVN.cpp index f038cbb..ec1985c 100644 --- a/llvm/lib/Transforms/Scalar/NewGVN.cpp +++ b/llvm/lib/Transforms/Scalar/NewGVN.cpp @@ -2207,7 +2207,7 @@ Value *NewGVN::getNextValueLeader(CongruenceClass *CC) const { // // - I must be moving to NewClass from OldClass // - The StoreCount of OldClass and NewClass is expected to have been updated -// for I already if it is is a store. +// for I already if it is a store. // - The OldClass memory leader has not been updated yet if I was the leader. void NewGVN::moveMemoryToNewCongruenceClass(Instruction *I, MemoryAccess *InstMA, -- 2.7.4