From 9fe9816bcd72e5ae5fe374d7483e4b5b0c618b22 Mon Sep 17 00:00:00 2001 From: Wilco Dijkstra Date: Wed, 21 Jun 2017 10:48:51 +0000 Subject: [PATCH] Emit SIMD moves as mov SIMD moves are currently emitted as ORR. Change this to use the MOV pseudo instruction just like integer moves (the ARM-ARM states MOV is the preferred disassembly), improving readability of -S output. gcc/ * config/aarch64/aarch64.md (movti_aarch64): Emit mov rather than orr. (movtf_aarch64): Likewise. * config/aarch64/aarch64-simd.md (aarch64_simd_mov): Emit mov rather than orr. From-SVN: r249444 --- gcc/ChangeLog | 8 ++++++++ gcc/config/aarch64/aarch64-simd.md | 4 ++-- gcc/config/aarch64/aarch64.md | 4 ++-- 3 files changed, 12 insertions(+), 4 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1fc622b..c9ee703 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,13 @@ 2017-06-21 Wilco Dijkstra + * config/aarch64/aarch64.md (movti_aarch64): + Emit mov rather than orr. + (movtf_aarch64): Likewise. + * config/aarch64/aarch64-simd.md (aarch64_simd_mov): + Emit mov rather than orr. + +2017-06-21 Wilco Dijkstra + * config/aarch64/aarch64-simd.md (aarch64_simd_dup): Swap alternatives, make integer dup more expensive. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index c949465..264a9c0 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -105,7 +105,7 @@ { case 0: return "ldr\\t%d0, %1"; case 1: return "str\\t%d1, %0"; - case 2: return "orr\t%0., %1., %1."; + case 2: return "mov\t%0., %1."; case 3: return "umov\t%0, %1.d[0]"; case 4: return "fmov\t%d0, %1"; case 5: return "mov\t%0, %1"; @@ -136,7 +136,7 @@ case 1: return "str\\t%q1, %0"; case 2: - return "orr\t%0., %1., %1."; + return "mov\t%0., %1."; case 3: case 4: case 5: diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 1a721bf..6bdbf65 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -1017,7 +1017,7 @@ # # # - orr\\t%0.16b, %1.16b, %1.16b + mov\\t%0.16b, %1.16b ldp\\t%0, %H0, %1 stp\\t%1, %H1, %0 stp\\txzr, xzr, %0 @@ -1131,7 +1131,7 @@ "TARGET_FLOAT && (register_operand (operands[0], TFmode) || aarch64_reg_or_fp_zero (operands[1], TFmode))" "@ - orr\\t%0.16b, %1.16b, %1.16b + mov\\t%0.16b, %1.16b # # # -- 2.7.4