From 9fac2a193e4553d6ce093a626ef5920c362d0753 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 3 Jul 2022 01:12:21 +0200 Subject: [PATCH] dt-bindings: mtd: intel: lgm-nand: Fix maximum chip select value The Intel LGM NAND IP only supports two chip selects: There's only two CS and ADDR_SEL register sets. Fix the maximum allowed chip select value according to the dt-bindings. Fixes: 2f9cea8eae44f5 ("dt-bindings: mtd: Add Nand Flash Controller support for Intel LGM SoC") Acked-by: Rob Herring Signed-off-by: Martin Blumenstingl Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20220702231227.1579176-3-martin.blumenstingl@googlemail.com --- Documentation/devicetree/bindings/mtd/intel,lgm-ebunand.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mtd/intel,lgm-ebunand.yaml b/Documentation/devicetree/bindings/mtd/intel,lgm-ebunand.yaml index 763ee3e..04f2619 100644 --- a/Documentation/devicetree/bindings/mtd/intel,lgm-ebunand.yaml +++ b/Documentation/devicetree/bindings/mtd/intel,lgm-ebunand.yaml @@ -51,7 +51,7 @@ patternProperties: properties: reg: minimum: 0 - maximum: 7 + maximum: 1 nand-ecc-mode: true -- 2.7.4