From 9f6861449457046cfff468613ddd14ed8a6e12fb Mon Sep 17 00:00:00 2001 From: Sanjay Patel Date: Wed, 1 May 2019 17:34:30 +0000 Subject: [PATCH] [PowerPC] add test that could infinite loop with reordered transforms; NFC This is a slightly reduced version of the test from D61384. Adding this as a preliminary step, so I can update D61149 with the proposed fix. llvm-svn: 359709 --- llvm/test/CodeGen/PowerPC/repeated-fp-divisors.ll | 27 +++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 llvm/test/CodeGen/PowerPC/repeated-fp-divisors.ll diff --git a/llvm/test/CodeGen/PowerPC/repeated-fp-divisors.ll b/llvm/test/CodeGen/PowerPC/repeated-fp-divisors.ll new file mode 100644 index 0000000..bb30a77 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/repeated-fp-divisors.ll @@ -0,0 +1,27 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- < %s | FileCheck %s + +define <4 x float> @repeated_fp_divisor(float %a, <4 x float> %b) { +; CHECK-LABEL: repeated_fp_divisor: +; CHECK: # %bb.0: +; CHECK-NEXT: xscvdpspn 0, 1 +; CHECK-NEXT: addis 3, 2, .LCPI0_0@toc@ha +; CHECK-NEXT: addi 3, 3, .LCPI0_0@toc@l +; CHECK-NEXT: lvx 3, 0, 3 +; CHECK-NEXT: addis 3, 2, .LCPI0_1@toc@ha +; CHECK-NEXT: addi 3, 3, .LCPI0_1@toc@l +; CHECK-NEXT: lvx 4, 0, 3 +; CHECK-NEXT: xxspltw 0, 0, 0 +; CHECK-NEXT: xvresp 1, 0 +; CHECK-NEXT: xvnmsubasp 35, 1, 0 +; CHECK-NEXT: xvmulsp 0, 34, 36 +; CHECK-NEXT: xvmaddasp 1, 1, 35 +; CHECK-NEXT: xvmulsp 34, 0, 1 +; CHECK-NEXT: blr + %ins = insertelement <4 x float> undef, float %a, i32 0 + %splat = shufflevector <4 x float> %ins, <4 x float> undef, <4 x i32> zeroinitializer + %t1 = fmul fast <4 x float> %b, + %mul = fdiv fast <4 x float> %t1, %splat + ret <4 x float> %mul +} + -- 2.7.4