From 9f5c8ff0ae893d6b936741977696aa81a106bf57 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Mon, 19 Oct 2020 09:29:19 -0700 Subject: [PATCH] freedreno: Rework GMEM limit init Split out into helper that can be re-used by gmemtool, to de-duplicate the limits table. And convert to switch instead of if-else ladder. A little bit of duplication, but that will no longer be the case with additional limits added in next patch. Signed-off-by: Rob Clark Part-of: --- src/gallium/drivers/freedreno/freedreno_gmem.c | 38 ++++++++++++++++++++++++ src/gallium/drivers/freedreno/freedreno_gmem.h | 1 + src/gallium/drivers/freedreno/freedreno_screen.c | 16 +--------- src/gallium/drivers/freedreno/gmemtool.c | 24 +++++---------- 4 files changed, 48 insertions(+), 31 deletions(-) diff --git a/src/gallium/drivers/freedreno/freedreno_gmem.c b/src/gallium/drivers/freedreno/freedreno_gmem.c index 7f6d330..b803c0a 100644 --- a/src/gallium/drivers/freedreno/freedreno_gmem.c +++ b/src/gallium/drivers/freedreno/freedreno_gmem.c @@ -780,6 +780,44 @@ fd_gmem_needs_restore(struct fd_batch *batch, const struct fd_tile *tile, } void +fd_gmem_init_limits(struct pipe_screen *pscreen) +{ + struct fd_screen *screen = fd_screen(pscreen); + + switch (screen->gpu_id) { + case 600 ... 699: + screen->gmem_alignw = 16; + screen->gmem_alignh = 4; + screen->tile_alignw = is_a650(screen) ? 96 : 32; + screen->tile_alignh = 32; + screen->num_vsc_pipes = 32; + break; + case 500 ... 599: + screen->gmem_alignw = screen->tile_alignw = 64; + screen->gmem_alignh = screen->tile_alignh = 32; + screen->num_vsc_pipes = 16; + break; + case 400 ... 499: + screen->gmem_alignw = screen->tile_alignw = 32; + screen->gmem_alignh = screen->tile_alignh = 32; + screen->num_vsc_pipes = 8; + break; + case 300 ... 399: + screen->gmem_alignw = screen->tile_alignw = 32; + screen->gmem_alignh = screen->tile_alignh = 32; + screen->num_vsc_pipes = 8; + break; + case 200 ... 299: + screen->gmem_alignw = screen->tile_alignw = 32; + screen->gmem_alignh = screen->tile_alignh = 32; + screen->num_vsc_pipes = 8; + break; + default: + unreachable("unsupported GPU"); + } +} + +void fd_gmem_screen_init(struct pipe_screen *pscreen) { struct fd_gmem_cache *cache = &fd_screen(pscreen)->gmem_cache; diff --git a/src/gallium/drivers/freedreno/freedreno_gmem.h b/src/gallium/drivers/freedreno/freedreno_gmem.h index 6a98e26..1ea4da8 100644 --- a/src/gallium/drivers/freedreno/freedreno_gmem.h +++ b/src/gallium/drivers/freedreno/freedreno_gmem.h @@ -93,6 +93,7 @@ bool fd_gmem_needs_restore(struct fd_batch *batch, const struct fd_tile *tile, uint32_t buffers); struct pipe_screen; +void fd_gmem_init_limits(struct pipe_screen *pscreen); void fd_gmem_screen_init(struct pipe_screen *pscreen); void fd_gmem_screen_fini(struct pipe_screen *pscreen); diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c index 08dbcf5..e4c4e61 100644 --- a/src/gallium/drivers/freedreno/freedreno_screen.c +++ b/src/gallium/drivers/freedreno/freedreno_screen.c @@ -992,21 +992,7 @@ fd_screen_create(struct fd_device *dev, struct renderonly *ro) goto fail; } - if (screen->gpu_id >= 600) { - screen->gmem_alignw = 16; - screen->gmem_alignh = 4; - screen->tile_alignw = is_a650(screen) ? 96 : 32; - screen->tile_alignh = 32; - screen->num_vsc_pipes = 32; - } else if (screen->gpu_id >= 500) { - screen->gmem_alignw = screen->tile_alignw = 64; - screen->gmem_alignh = screen->tile_alignh = 32; - screen->num_vsc_pipes = 16; - } else { - screen->gmem_alignw = screen->tile_alignw = 32; - screen->gmem_alignh = screen->tile_alignh = 32; - screen->num_vsc_pipes = 8; - } + fd_gmem_init_limits(pscreen); if (fd_mesa_debug & FD_DBG_PERFC) { screen->perfcntr_groups = fd_perfcntrs(screen->gpu_id, diff --git a/src/gallium/drivers/freedreno/gmemtool.c b/src/gallium/drivers/freedreno/gmemtool.c index 983936f..faa01a9 100644 --- a/src/gallium/drivers/freedreno/gmemtool.c +++ b/src/gallium/drivers/freedreno/gmemtool.c @@ -80,11 +80,6 @@ static const struct gmem_key keys[] = { struct gpu_info { const char *name; uint32_t gpu_id; - uint32_t gmem_alignw; - uint32_t gmem_alignh; - uint32_t tile_alignw; - uint32_t tile_alignh; - uint32_t num_vsc_pipes; uint8_t gmem_page_align; uint32_t gmemsize_bytes; }; @@ -96,12 +91,12 @@ struct gpu_info { /* keep sorted by gpu name: */ static const struct gpu_info gpu_infos[] = { - { "a306", 307, 32, 32, 32, 32, 8, 4, SZ_128K }, - { "a405", 405, 32, 32, 32, 32, 8, 4, SZ_256K }, - { "a530", 530, 64, 32, 64, 32, 16, 4, SZ_1M }, - { "a618", 618, 16, 4, 32, 32, 32, 1, SZ_512K }, - { "a630", 630, 16, 4, 32, 32, 32, 1, SZ_1M }, - { "a650", 630, 16, 4, 96, 32, 32, 1, SZ_1M + SZ_128K }, + { "a306", 307, 4, SZ_128K }, + { "a405", 405, 4, SZ_256K }, + { "a530", 530, 4, SZ_1M }, + { "a618", 618, 1, SZ_512K }, + { "a630", 630, 1, SZ_1M }, + { "a650", 630, 1, SZ_1M + SZ_128K }, }; @@ -168,14 +163,11 @@ main(int argc, char **argv) */ struct fd_screen screen = { .gpu_id = gpu_info->gpu_id, - .gmem_alignw = gpu_info->gmem_alignw, - .gmem_alignh = gpu_info->gmem_alignh, - .tile_alignw = gpu_info->tile_alignw, - .tile_alignh = gpu_info->tile_alignh, - .num_vsc_pipes = gpu_info->num_vsc_pipes, .gmemsize_bytes = gpu_info->gmemsize_bytes, }; + fd_gmem_init_limits(&screen.base); + /* And finally run thru all the GMEM keys: */ for (int i = 0; i < ARRAY_SIZE(keys); i++) { struct gmem_key key = keys[i]; -- 2.7.4