From 9f405b0162ba92bf8317ce1329aad96fecc89273 Mon Sep 17 00:00:00 2001 From: Ping-Ke Shih Date: Fri, 8 Apr 2022 08:13:44 +0800 Subject: [PATCH] rtw89: ser: configure top ERR IMR for firmware to recover Turn on ERR IMR, and then firmware can capture interrupts reflecting errors to recover hardware states. Signed-off-by: Ping-Ke Shih Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20220408001353.17188-5-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/mac.c | 15 +++++++++++++++ drivers/net/wireless/realtek/rtw89/reg.h | 29 +++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+) diff --git a/drivers/net/wireless/realtek/rtw89/mac.c b/drivers/net/wireless/realtek/rtw89/mac.c index c10eca4..2346350 100644 --- a/drivers/net/wireless/realtek/rtw89/mac.c +++ b/drivers/net/wireless/realtek/rtw89/mac.c @@ -2842,6 +2842,19 @@ static int rtw89_mac_enable_imr(struct rtw89_dev *rtwdev, u8 mac_idx, return 0; } +static void rtw89_mac_err_imr_ctrl(struct rtw89_dev *rtwdev, bool en) +{ + enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; + + rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR, + en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS); + rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR, + en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS); + if (chip_id != RTL8852B && rtwdev->mac.dle_info.c1_rx_qta) + rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1, + en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS); +} + static int rtw89_mac_dbcc_enable(struct rtw89_dev *rtwdev, bool enable) { int ret = 0; @@ -2923,6 +2936,8 @@ static int rtw89_mac_trx_init(struct rtw89_dev *rtwdev) return ret; } + rtw89_mac_err_imr_ctrl(rtwdev, true); + ret = set_host_rpr(rtwdev); if (ret) { rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h index 3d66d35..e5f8374 100644 --- a/drivers/net/wireless/realtek/rtw89/reg.h +++ b/drivers/net/wireless/realtek/rtw89/reg.h @@ -504,6 +504,21 @@ #define B_AX_WDE_EMPTY_QUE_CMAC0_MBH BIT(1) #define B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC BIT(0) +#define R_AX_DMAC_ERR_IMR 0x8520 +#define B_AX_DLE_CPUIO_ERR_INT_EN BIT(10) +#define B_AX_APB_BRIDGE_ERR_INT_EN BIT(9) +#define B_AX_DISPATCH_ERR_INT_EN BIT(8) +#define B_AX_PKTIN_ERR_INT_EN BIT(7) +#define B_AX_PLE_DLE_ERR_INT_EN BIT(6) +#define B_AX_TXPKTCTRL_ERR_INT_EN BIT(5) +#define B_AX_WDE_DLE_ERR_INT_EN BIT(4) +#define B_AX_STA_SCHEDULER_ERR_INT_EN BIT(3) +#define B_AX_MPDU_ERR_INT_EN BIT(2) +#define B_AX_WSEC_ERR_INT_EN BIT(1) +#define B_AX_WDRLS_ERR_INT_EN BIT(0) +#define DMAC_ERR_IMR_EN GENMASK(31, 0) +#define DMAC_ERR_IMR_DIS 0 + #define R_AX_DMAC_ERR_ISR 0x8524 #define B_AX_DLE_CPUIO_ERR_FLAG BIT(10) #define B_AX_APB_BRIDGE_ERR_FLAG BIT(9) @@ -1805,6 +1820,20 @@ #define B_AX_TXSC_40M_MASK GENMASK(7, 4) #define B_AX_TXSC_20M_MASK GENMASK(3, 0) +#define R_AX_CMAC_ERR_IMR 0xC160 +#define R_AX_CMAC_ERR_IMR_C1 0xE160 +#define B_AX_WMAC_TX_ERR_IND_EN BIT(7) +#define B_AX_WMAC_RX_ERR_IND_EN BIT(6) +#define B_AX_TXPWR_CTRL_ERR_IND_EN BIT(5) +#define B_AX_PHYINTF_ERR_IND_EN BIT(4) +#define B_AX_DMA_TOP_ERR_IND_EN BIT(3) +#define B_AX_PTCL_TOP_ERR_IND_EN BIT(1) +#define B_AX_SCHEDULE_TOP_ERR_IND_EN BIT(0) +#define CMAC0_ERR_IMR_EN GENMASK(31, 0) +#define CMAC1_ERR_IMR_EN GENMASK(31, 0) +#define CMAC0_ERR_IMR_DIS 0 +#define CMAC1_ERR_IMR_DIS 0 + #define R_AX_CMAC_ERR_ISR 0xC164 #define R_AX_CMAC_ERR_ISR_C1 0xE164 #define B_AX_WMAC_TX_ERR_IND BIT(7) -- 2.7.4