From 9ec3e565d3cf6776d8cbf884a0090f1daa133027 Mon Sep 17 00:00:00 2001 From: Xingyu Wu Date: Fri, 13 Jan 2023 11:09:03 +0800 Subject: [PATCH] clk: starfive: Fixed UART3-5 error after resume Fixed UART3-5 error after hibernation by adjusting register shift. Signed-off-by: Xingyu Wu --- drivers/clk/starfive/clk-starfive-jh7110-gen.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/clk/starfive/clk-starfive-jh7110-gen.c b/drivers/clk/starfive/clk-starfive-jh7110-gen.c index 26cbe07..3a4d989 100644 --- a/drivers/clk/starfive/clk-starfive-jh7110-gen.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-gen.c @@ -79,11 +79,6 @@ static void jh7110_clk_reg_rmw(struct jh7110_clk *clk, u32 mask, u32 value) unsigned long flags; spin_lock_irqsave(&priv->rmw_lock, flags); - if ((clk->idx == JH7110_UART3_CLK_CORE - || clk->idx == JH7110_UART4_CLK_CORE - || clk->idx == JH7110_UART5_CLK_CORE) - && (value != JH7110_CLK_ENABLE)) - value <<= 8; value |= jh7110_clk_reg_get(clk) & ~mask; writel_relaxed(value, reg); spin_unlock_irqrestore(&priv->rmw_lock, flags); @@ -163,6 +158,12 @@ static int jh7110_clk_set_rate(struct clk_hw *hw, unsigned long div = clamp(DIV_ROUND_CLOSEST(parent_rate, rate), 1UL, (unsigned long)clk->max_div); + /* UART3-5: [15:8]: integer part of the divisor. [7:0] fraction part of the divisor */ + if (clk->idx == JH7110_UART3_CLK_CORE || + clk->idx == JH7110_UART4_CLK_CORE || + clk->idx == JH7110_UART5_CLK_CORE) + div <<= 8; + jh7110_clk_reg_rmw(clk, JH7110_CLK_DIV_MASK, div); return 0; } -- 2.7.4