From 9e2d14c2851269928df28a38c76d4d87536bcd49 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Tue, 31 Aug 2021 10:49:42 +0100 Subject: [PATCH] [X86] Copy X86SchedSkylakeServer.td to X86SchedIceLake.td Icelake, Rocketlake and Tigerlake targets currently use the SkylakeServer scheduler model, despite being a later microarchitecture, leading to both reported bugs (PR48110) and discrepancies when comparing llvm-mca reports to other profiling tools (OSACA, uops, uica, etc.). And tbh I'm getting sick of llvm-mca getting blamed for what are backend scheduler model issues :-( This patch doesn't attempt to fix any of these discrepancies - there should be no changes in codegen - its a setup patch that copies the skx model, renames all the resources, adds the additional ports (but doesn't reference them yet) and updates the llvm-exegesis pfm counter mappings (based off https://sourceforge.net/p/perfmon2/libpfm4/ci/master/tree/lib/events/intel_icl_events.h). This should make it trivial for anyone with hardware access to use llvm-exegesis reports to iteratively improve the model (my attempts to get hold of a cheap tiger lake box haven't been fruitful yet....). I will copy the SkylakeServer llvm-mca resource tests as follow up commits - the diff should entirely be the resource renames. Differential Revision: https://reviews.llvm.org/D108914 --- llvm/lib/Target/X86/X86.td | 9 +- llvm/lib/Target/X86/X86PfmCounters.td | 20 +- llvm/lib/Target/X86/X86SchedIceLake.td | 2636 ++++++++++++++++++++++++++++++++ 3 files changed, 2659 insertions(+), 6 deletions(-) create mode 100644 llvm/lib/Target/X86/X86SchedIceLake.td diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td index 48e2e87..2358de8 100644 --- a/llvm/lib/Target/X86/X86.td +++ b/llvm/lib/Target/X86/X86.td @@ -612,6 +612,7 @@ include "X86ScheduleBdVer2.td" include "X86ScheduleBtVer2.td" include "X86SchedSkylakeClient.td" include "X86SchedSkylakeServer.td" +include "X86SchedIceLake.td" //===----------------------------------------------------------------------===// // X86 Processor Feature Lists @@ -1372,13 +1373,13 @@ def : ProcModel<"cooperlake", SkylakeServerModel, ProcessorFeatures.CPXFeatures, ProcessorFeatures.CPXTuning>; def : ProcModel<"cannonlake", SkylakeServerModel, ProcessorFeatures.CNLFeatures, ProcessorFeatures.CNLTuning>; -def : ProcModel<"icelake-client", SkylakeServerModel, +def : ProcModel<"icelake-client", IceLakeModel, ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>; -def : ProcModel<"rocketlake", SkylakeServerModel, +def : ProcModel<"rocketlake", IceLakeModel, ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>; -def : ProcModel<"icelake-server", SkylakeServerModel, +def : ProcModel<"icelake-server", IceLakeModel, ProcessorFeatures.ICXFeatures, ProcessorFeatures.ICXTuning>; -def : ProcModel<"tigerlake", SkylakeServerModel, +def : ProcModel<"tigerlake", IceLakeModel, ProcessorFeatures.TGLFeatures, ProcessorFeatures.TGLTuning>; def : ProcModel<"sapphirerapids", SkylakeServerModel, ProcessorFeatures.SPRFeatures, ProcessorFeatures.SPRTuning>; diff --git a/llvm/lib/Target/X86/X86PfmCounters.td b/llvm/lib/Target/X86/X86PfmCounters.td index 3844667..25fcba1 100644 --- a/llvm/lib/Target/X86/X86PfmCounters.td +++ b/llvm/lib/Target/X86/X86PfmCounters.td @@ -142,8 +142,24 @@ def SkylakeServerPfmCounters : ProcPfmCounters { def : PfmCountersBinding<"skylake-avx512", SkylakeServerPfmCounters>; def : PfmCountersBinding<"cascadelake", SkylakeServerPfmCounters>; def : PfmCountersBinding<"cannonlake", SkylakeServerPfmCounters>; -def : PfmCountersBinding<"icelake-client", SkylakeServerPfmCounters>; -def : PfmCountersBinding<"icelake-server", SkylakeServerPfmCounters>; + +def IceLakePfmCounters : ProcPfmCounters { + let CycleCounter = UnhaltedCoreCyclesPfmCounter; + let UopsCounter = UopsIssuedPfmCounter; + let IssueCounters = [ + PfmIssueCounter<"ICXPort0", "uops_dispatched_port:port_0">, + PfmIssueCounter<"ICXPort1", "uops_dispatched_port:port_1">, + PfmIssueCounter<"ICXPort23", "uops_dispatched_port:port_2_3">, + PfmIssueCounter<"ICXPort49", "uops_dispatched_port:port_4_9">, + PfmIssueCounter<"ICXPort5", "uops_dispatched_port:port_5">, + PfmIssueCounter<"ICXPort6", "uops_dispatched_port:port_6">, + PfmIssueCounter<"ICXPort78", "uops_dispatched_port:port_7_8"> + ]; +} +def : PfmCountersBinding<"icelake-client", IceLakePfmCounters>; +def : PfmCountersBinding<"icelake-server", IceLakePfmCounters>; +def : PfmCountersBinding<"rocketlake", IceLakePfmCounters>; +def : PfmCountersBinding<"tigerlake", IceLakePfmCounters>; // AMD X86 Counters. // Set basic counters for AMD cpus that we know libpfm4 supports. diff --git a/llvm/lib/Target/X86/X86SchedIceLake.td b/llvm/lib/Target/X86/X86SchedIceLake.td new file mode 100644 index 0000000..5561ccf --- /dev/null +++ b/llvm/lib/Target/X86/X86SchedIceLake.td @@ -0,0 +1,2636 @@ +//=- X86SchedIceLake.td - X86 Ice Lake Scheduling ------------*- tablegen -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file defines the machine model for Ice Lake to support +// instruction scheduling and other instruction cost heuristics. +// +// TODO: This is mainly a copy X86SchedSkylakeServer.td, but allows us to +// iteratively improve scheduling handling toward better modelling the +// Ice Lake (Sunny/Cypress Cove) microarchitecture. +// +//===----------------------------------------------------------------------===// + +def IceLakeModel : SchedMachineModel { + // All x86 instructions are modeled as a single micro-op, and Ice Lake can + // decode 6 instructions per cycle. + let IssueWidth = 6; + let MicroOpBufferSize = 224; // Based on the reorder buffer. + let LoadLatency = 5; + let MispredictPenalty = 14; + + // Based on the LSD (loop-stream detector) queue size and benchmarking data. + let LoopMicroOpBufferSize = 50; + + // This flag is set to allow the scheduler to assign a default model to + // unrecognized opcodes. + let CompleteModel = 0; +} + +let SchedModel = IceLakeModel in { + +// Ice Lake can issue micro-ops to 8 different ports in one cycle. + +// Ports 0, 1, 5, and 6 handle all computation. +// Ports 4 and 9 gets the data half of stores. Store data can be available later +// than the store address, but since we don't model the latency of stores, we +// can ignore that. +// Ports 2 and 3 are identical. They handle loads and address calculations. +// Ports 7 and 8 are identical. They handle stores address calculations. +def ICXPort0 : ProcResource<1>; +def ICXPort1 : ProcResource<1>; +def ICXPort2 : ProcResource<1>; +def ICXPort3 : ProcResource<1>; +def ICXPort4 : ProcResource<1>; +def ICXPort5 : ProcResource<1>; +def ICXPort6 : ProcResource<1>; +def ICXPort7 : ProcResource<1>; +def ICXPort8 : ProcResource<1>; +def ICXPort9 : ProcResource<1>; + +// Many micro-ops are capable of issuing on multiple ports. +def ICXPort01 : ProcResGroup<[ICXPort0, ICXPort1]>; +def ICXPort23 : ProcResGroup<[ICXPort2, ICXPort3]>; +def ICXPort237 : ProcResGroup<[ICXPort2, ICXPort3, ICXPort7]>; +def ICXPort04 : ProcResGroup<[ICXPort0, ICXPort4]>; +def ICXPort05 : ProcResGroup<[ICXPort0, ICXPort5]>; +def ICXPort06 : ProcResGroup<[ICXPort0, ICXPort6]>; +def ICXPort15 : ProcResGroup<[ICXPort1, ICXPort5]>; +def ICXPort16 : ProcResGroup<[ICXPort1, ICXPort6]>; +def ICXPort49 : ProcResGroup<[ICXPort4, ICXPort9]>; +def ICXPort56 : ProcResGroup<[ICXPort5, ICXPort6]>; +def ICXPort78 : ProcResGroup<[ICXPort7, ICXPort8]>; +def ICXPort015 : ProcResGroup<[ICXPort0, ICXPort1, ICXPort5]>; +def ICXPort056 : ProcResGroup<[ICXPort0, ICXPort5, ICXPort6]>; +def ICXPort0156: ProcResGroup<[ICXPort0, ICXPort1, ICXPort5, ICXPort6]>; + +def ICXDivider : ProcResource<1>; // Integer division issued on port 0. +// FP division and sqrt on port 0. +def ICXFPDivider : ProcResource<1>; + +// 60 Entry Unified Scheduler +def ICXPortAny : ProcResGroup<[ICXPort0, ICXPort1, ICXPort2, ICXPort3, ICXPort4, + ICXPort5, ICXPort6, ICXPort7, ICXPort8, ICXPort9]> { + let BufferSize=60; +} + +// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5 +// cycles after the memory operand. +def : ReadAdvance; + +// Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available +// until 5/6/7 cycles after the memory operand. +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; + +def : ReadAdvance; + +// Many SchedWrites are defined in pairs with and without a folded load. +// Instructions with folded loads are usually micro-fused, so they only appear +// as two micro-ops when queued in the reservation station. +// This multiclass defines the resource usage for variants with and without +// folded loads. +multiclass ICXWriteResPair ExePorts, + int Lat, list Res = [1], int UOps = 1, + int LoadLat = 5> { + // Register variant is using a single cycle on ExePort. + def : WriteRes { + let Latency = Lat; + let ResourceCycles = Res; + let NumMicroOps = UOps; + } + + // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to + // the latency (default = 5). + def : WriteRes { + let Latency = !add(Lat, LoadLat); + let ResourceCycles = !listconcat([1], Res); + let NumMicroOps = !add(UOps, 1); + } +} + +// A folded store needs a cycle on port 4 for the store data, and an extra port +// 2/3/7 cycle to recompute the address. +def : WriteRes; + +// Arithmetic. +defm : ICXWriteResPair; // Simple integer ALU op. +defm : ICXWriteResPair; // Integer ALU + flags op. + +// Integer multiplication. +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; +def ICXWriteIMulH : WriteRes { let Latency = 4; } +def : WriteRes { + let Latency = !add(ICXWriteIMulH.Latency, SkylakeServerModel.LoadLatency); +} + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +// TODO: Why isn't the ICXDivider used? +defm : ICXWriteResPair; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : ICXWriteResPair; + +def : WriteRes; // LEA instructions can't fold loads. + +defm : ICXWriteResPair; // Conditional move. +defm : X86WriteRes; // x87 conditional move. +def : WriteRes; // Setcc. +def : WriteRes { + let Latency = 2; + let NumMicroOps = 3; +} +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +// Integer shifts and rotates. +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; + +// SHLD/SHRD. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +// Bit counts. +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; + +// BMI1 BEXTR/BLS, BMI2 BZHI +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; + +// Loads, stores, and moves, not folded with other operations. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +// Model the effect of clobbering the read-write mask operand of the GATHER operation. +// Does not cost anything by itself, only has latency, matching that of the WriteLoad, +defm : X86WriteRes; + +// Idioms that clear a register, like xorps %xmm0, %xmm0. +// These can often bypass execution ports completely. +def : WriteRes; + +// Branches don't produce values, so they have no latency, but they still +// consume resources. Indirect branches can fold loads. +defm : ICXWriteResPair; + +// Floating point. This covers both scalar and vector operations. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : ICXWriteResPair; // Floating point add/sub. +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; // Floating point double add/sub. +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; + +defm : ICXWriteResPair; // Floating point compare. +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; // Floating point double compare. +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; + +defm : ICXWriteResPair; // Floating point compare to flags (X87). +defm : ICXWriteResPair; // Floating point compare to flags (SSE). + +defm : ICXWriteResPair; // Floating point multiplication. +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; // Floating point double multiplication. +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; + +defm : ICXWriteResPair; // 10-14 cycles. // Floating point division. +//defm : ICXWriteResPair; // 10-14 cycles. +defm : ICXWriteResPair; // 10-14 cycles. +defm : ICXWriteResPair; // 10-14 cycles. +//defm : ICXWriteResPair; // 10-14 cycles. // Floating point division. +//defm : ICXWriteResPair; // 10-14 cycles. +//defm : ICXWriteResPair; // 10-14 cycles. +defm : ICXWriteResPair; // 10-14 cycles. + +defm : ICXWriteResPair; // Floating point square root. +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; // Floating point double square root. +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; // Floating point long double square root. + +defm : ICXWriteResPair; // Floating point reciprocal estimate. +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; + +defm : ICXWriteResPair; // Floating point reciprocal square root estimate. +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; + +defm : ICXWriteResPair; // Fused Multiply Add. +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; // Floating point double dot product. +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; // Floating point fabs/fchs. +defm : ICXWriteResPair; // Floating point rounding. +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; // Floating point and/or/xor logicals. +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; // Floating point TEST instructions. +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; // Floating point vector shuffles. +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; // Floating point vector variable shuffles. +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; // Floating point vector blends. +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; // Fp vector variable blends. +defm : ICXWriteResPair; +defm : ICXWriteResPair; + +// FMA Scheduling helper class. +// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; } + +// Vector integer operations. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : ICXWriteResPair; // Vector integer ALU op, no logicals. +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; // Vector integer and/or/xor. +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; // Vector integer TEST instructions. +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; // Vector integer multiply. +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; // Vector PMULLD. +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; // Vector shuffles. +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; // Vector variable shuffles. +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; // Vector blends. +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; // Vector variable blends. +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; // Vector MPSAD. +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; // Vector PSADBW. +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; // Vector PHMINPOS. + +// Vector integer shifts. +defm : ICXWriteResPair; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : ICXWriteResPair; +defm : ICXWriteResPair; // Vector integer immediate shifts. +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; // Variable vector shifts. +defm : ICXWriteResPair; +defm : ICXWriteResPair; + +// Vector insert/extract operations. +def : WriteRes { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def : WriteRes { + let Latency = 6; + let NumMicroOps = 2; +} +def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>; + +def : WriteRes { + let Latency = 3; + let NumMicroOps = 2; +} +def : WriteRes { + let Latency = 2; + let NumMicroOps = 3; +} + +// Conversion between integer and float. +defm : ICXWriteResPair; // Needs more work: DD vs DQ. +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; + +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; // Needs more work: DD vs DQ. +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; + +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +// Strings instructions. + +// Packed Compare Implicit Length Strings, Return Mask +def : WriteRes { + let Latency = 10; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def : WriteRes { + let Latency = 16; + let NumMicroOps = 4; + let ResourceCycles = [3,1]; +} + +// Packed Compare Explicit Length Strings, Return Mask +def : WriteRes { + let Latency = 19; + let NumMicroOps = 9; + let ResourceCycles = [4,3,1,1]; +} +def : WriteRes { + let Latency = 25; + let NumMicroOps = 10; + let ResourceCycles = [4,3,1,1,1]; +} + +// Packed Compare Implicit Length Strings, Return Index +def : WriteRes { + let Latency = 10; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def : WriteRes { + let Latency = 16; + let NumMicroOps = 4; + let ResourceCycles = [3,1]; +} + +// Packed Compare Explicit Length Strings, Return Index +def : WriteRes { + let Latency = 18; + let NumMicroOps = 8; + let ResourceCycles = [4,3,1]; +} +def : WriteRes { + let Latency = 24; + let NumMicroOps = 9; + let ResourceCycles = [4,3,1,1]; +} + +// MOVMSK Instructions. +def : WriteRes { let Latency = 2; } +def : WriteRes { let Latency = 2; } +def : WriteRes { let Latency = 2; } +def : WriteRes { let Latency = 2; } + +// AES instructions. +def : WriteRes { // Decryption, encryption. + let Latency = 4; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def : WriteRes { + let Latency = 10; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} + +def : WriteRes { // InvMixColumn. + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def : WriteRes { + let Latency = 14; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} + +def : WriteRes { // Key Generation. + let Latency = 20; + let NumMicroOps = 11; + let ResourceCycles = [3,6,2]; +} +def : WriteRes { + let Latency = 25; + let NumMicroOps = 11; + let ResourceCycles = [3,6,1,1]; +} + +// Carry-less multiplication instructions. +def : WriteRes { + let Latency = 6; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def : WriteRes { + let Latency = 12; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} + +// Catch-all for expensive system instructions. +def : WriteRes { let Latency = 100; } // def WriteSystem : SchedWrite; + +// AVX2. +defm : ICXWriteResPair; // Fp 256-bit width vector shuffles. +defm : ICXWriteResPair; // Fp 256-bit width vector variable shuffles. +defm : ICXWriteResPair; // 256-bit width vector shuffles. +defm : ICXWriteResPair; // 256-bit width packed vector width-changing move. +defm : ICXWriteResPair; // 256-bit width vector variable shuffles. + +// Old microcoded instructions that nobody use. +def : WriteRes { let Latency = 100; } // def WriteMicrocoded : SchedWrite; + +// Fence instructions. +def : WriteRes; + +// Load/store MXCSR. +def : WriteRes { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } +def : WriteRes { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } + +// Nop, not very useful expect it provides a model for nops! +def : WriteRes; + +//////////////////////////////////////////////////////////////////////////////// +// Horizontal add/sub instructions. +//////////////////////////////////////////////////////////////////////////////// + +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; +defm : ICXWriteResPair; + +// Remaining instrs. + +def ICXWriteResGroup1 : SchedWriteRes<[ICXPort0]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[ICXWriteResGroup1], (instregex "KAND(B|D|Q|W)rr", + "KANDN(B|D|Q|W)rr", + "KMOV(B|D|Q|W)kk", + "KNOT(B|D|Q|W)rr", + "KOR(B|D|Q|W)rr", + "KXNOR(B|D|Q|W)rr", + "KXOR(B|D|Q|W)rr", + "KSET0(B|D|Q|W)", // Same as KXOR + "KSET1(B|D|Q|W)", // Same as KXNOR + "MMX_PADDS(B|W)irr", + "MMX_PADDUS(B|W)irr", + "MMX_PAVG(B|W)irr", + "MMX_PCMPEQ(B|D|W)irr", + "MMX_PCMPGT(B|D|W)irr", + "MMX_P(MAX|MIN)SWirr", + "MMX_P(MAX|MIN)UBirr", + "MMX_PSUBS(B|W)irr", + "MMX_PSUBUS(B|W)irr", + "VPMOVB2M(Z|Z128|Z256)rr", + "VPMOVD2M(Z|Z128|Z256)rr", + "VPMOVQ2M(Z|Z128|Z256)rr", + "VPMOVW2M(Z|Z128|Z256)rr")>; + +def ICXWriteResGroup3 : SchedWriteRes<[ICXPort5]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[ICXWriteResGroup3], (instregex "COM(P?)_FST0r", + "KMOV(B|D|Q|W)kr", + "UCOM_F(P?)r")>; + +def ICXWriteResGroup4 : SchedWriteRes<[ICXPort6]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[ICXWriteResGroup4], (instregex "JMP(16|32|64)r")>; + +def ICXWriteResGroup6 : SchedWriteRes<[ICXPort05]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[ICXWriteResGroup6], (instrs FINCSTP, FNOP)>; + +def ICXWriteResGroup7 : SchedWriteRes<[ICXPort06]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[ICXWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>; + +def ICXWriteResGroup8 : SchedWriteRes<[ICXPort15]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[ICXWriteResGroup8], (instregex "ANDN(32|64)rr")>; + +def ICXWriteResGroup9 : SchedWriteRes<[ICXPort015]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[ICXWriteResGroup9], (instregex "VBLENDMPD(Z128|Z256)rr", + "VBLENDMPS(Z128|Z256)rr", + "VPADD(B|D|Q|W)(Y|Z|Z128|Z256)rr", + "(V?)PADD(B|D|Q|W)rr", + "VPBLENDD(Y?)rri", + "VPBLENDMB(Z128|Z256)rr", + "VPBLENDMD(Z128|Z256)rr", + "VPBLENDMQ(Z128|Z256)rr", + "VPBLENDMW(Z128|Z256)rr", + "VPSUB(B|D|Q|W)(Y|Z|Z128|Z256)rrk", + "VPTERNLOGD(Z|Z128|Z256)rri", + "VPTERNLOGQ(Z|Z128|Z256)rri")>; + +def ICXWriteResGroup10 : SchedWriteRes<[ICXPort0156]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[ICXWriteResGroup10], (instrs CBW, CWDE, CDQE, + CMC, STC, + SGDT64m, + SIDT64m, + SMSW16m, + STRm, + SYSCALL)>; + +def ICXWriteResGroup11 : SchedWriteRes<[ICXPort4,ICXPort237]> { + let Latency = 1; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[ICXWriteResGroup11], (instrs FBSTPm, VMPTRSTm)>; +def: InstRW<[ICXWriteResGroup11], (instregex "KMOV(B|D|Q|W)mk", + "ST_FP(32|64|80)m")>; + +def ICXWriteResGroup13 : SchedWriteRes<[ICXPort5]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[ICXWriteResGroup13], (instrs MMX_MOVQ2DQrr)>; + +def ICXWriteResGroup14 : SchedWriteRes<[ICXPort05]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[ICXWriteResGroup14], (instrs FDECSTP, + MMX_MOVDQ2Qrr)>; + +def ICXWriteResGroup17 : SchedWriteRes<[ICXPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[ICXWriteResGroup17], (instrs LFENCE, + WAIT, + XGETBV)>; + +def ICXWriteResGroup20 : SchedWriteRes<[ICXPort6,ICXPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[ICXWriteResGroup20], (instregex "CLFLUSH")>; + +def ICXWriteResGroup21 : SchedWriteRes<[ICXPort237,ICXPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[ICXWriteResGroup21], (instrs SFENCE)>; + +def ICXWriteResGroup23 : SchedWriteRes<[ICXPort06,ICXPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[ICXWriteResGroup23], (instrs CWD, + JCXZ, JECXZ, JRCXZ, + ADC8i8, SBB8i8, + ADC16i16, SBB16i16, + ADC32i32, SBB32i32, + ADC64i32, SBB64i32)>; + +def ICXWriteResGroup25 : SchedWriteRes<[ICXPort4,ICXPort6,ICXPort237]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[ICXWriteResGroup25], (instrs FNSTCW16m)>; + +def ICXWriteResGroup27 : SchedWriteRes<[ICXPort4,ICXPort237,ICXPort15]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[ICXWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>; + +def ICXWriteResGroup28 : SchedWriteRes<[ICXPort4,ICXPort237,ICXPort0156]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[ICXWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8, + STOSB, STOSL, STOSQ, STOSW)>; +def: InstRW<[ICXWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>; + +def ICXWriteResGroup29 : SchedWriteRes<[ICXPort4,ICXPort237,ICXPort15]> { + let Latency = 2; + let NumMicroOps = 5; + let ResourceCycles = [2,2,1]; +} +def: InstRW<[ICXWriteResGroup29], (instregex "VMOVDQU8Zmr(b?)")>; + +def ICXWriteResGroup30 : SchedWriteRes<[ICXPort0]> { + let Latency = 3; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[ICXWriteResGroup30], (instregex "KMOV(B|D|Q|W)rk", + "KORTEST(B|D|Q|W)rr", + "KTEST(B|D|Q|W)rr")>; + +def ICXWriteResGroup31 : SchedWriteRes<[ICXPort1]> { + let Latency = 3; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[ICXWriteResGroup31], (instregex "PDEP(32|64)rr", + "PEXT(32|64)rr")>; + +def ICXWriteResGroup32 : SchedWriteRes<[ICXPort5]> { + let Latency = 3; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[ICXWriteResGroup32], (instrs VPSADBWZrr)>; // TODO: 512-bit ops require ports 0/1 to be joined. +def: InstRW<[ICXWriteResGroup32], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)", + "VALIGND(Z|Z128|Z256)rri", + "VALIGNQ(Z|Z128|Z256)rri", + "VDBPSADBWZrri", // TODO: 512-bit ops require ports 0/1 to be joined. + "VPBROADCAST(B|W)rr", + "VP(MAX|MIN)(S|U)Q(Z|Z128|Z256)rr")>; + +def ICXWriteResGroup33 : SchedWriteRes<[ICXPort5]> { + let Latency = 4; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[ICXWriteResGroup33], (instregex "KADD(B|D|Q|W)rr", + "KSHIFTL(B|D|Q|W)ri", + "KSHIFTR(B|D|Q|W)ri", + "KUNPCK(BW|DQ|WD)rr", + "VCMPPD(Z|Z128|Z256)rri", + "VCMPPS(Z|Z128|Z256)rri", + "VCMP(SD|SS)Zrr", + "VFPCLASS(PD|PS)(Z|Z128|Z256)rr", + "VFPCLASS(SD|SS)Zrr", + "VPCMPB(Z|Z128|Z256)rri", + "VPCMPD(Z|Z128|Z256)rri", + "VPCMPEQ(B|D|Q|W)(Z|Z128|Z256)rr", + "VPCMPGT(B|D|Q|W)(Z|Z128|Z256)rr", + "VPCMPQ(Z|Z128|Z256)rri", + "VPCMPU(B|D|Q|W)(Z|Z128|Z256)rri", + "VPCMPW(Z|Z128|Z256)rri", + "VPTEST(N?)M(B|D|Q|W)(Z|Z128|Z256)rr")>; + +def ICXWriteResGroup34 : SchedWriteRes<[ICXPort0,ICXPort0156]> { + let Latency = 3; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[ICXWriteResGroup34], (instrs FNSTSW16r)>; + +def ICXWriteResGroup37 : SchedWriteRes<[ICXPort0,ICXPort5]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[ICXWriteResGroup37], (instregex "MMX_PH(ADD|SUB)SWrr")>; + +def ICXWriteResGroup38 : SchedWriteRes<[ICXPort5,ICXPort01]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[ICXWriteResGroup38], (instregex "(V?)PH(ADD|SUB)SW(Y?)rr")>; + +def ICXWriteResGroup41 : SchedWriteRes<[ICXPort5,ICXPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[ICXWriteResGroup41], (instrs MMX_PACKSSDWirr, + MMX_PACKSSWBirr, + MMX_PACKUSWBirr)>; + +def ICXWriteResGroup42 : SchedWriteRes<[ICXPort6,ICXPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[ICXWriteResGroup42], (instregex "CLD")>; + +def ICXWriteResGroup43 : SchedWriteRes<[ICXPort237,ICXPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[ICXWriteResGroup43], (instrs MFENCE)>; + +def ICXWriteResGroup44 : SchedWriteRes<[ICXPort06,ICXPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[ICXWriteResGroup44], (instregex "RCL(8|16|32|64)r(1|i)", + "RCR(8|16|32|64)r(1|i)")>; + +def ICXWriteResGroup45 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort237]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[ICXWriteResGroup45], (instrs FNSTSWm)>; + +def ICXWriteResGroup47 : SchedWriteRes<[ICXPort4,ICXPort6,ICXPort237,ICXPort0156]> { + let Latency = 3; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[ICXWriteResGroup47], (instregex "CALL(16|32|64)r")>; + +def ICXWriteResGroup48 : SchedWriteRes<[ICXPort4,ICXPort237,ICXPort06,ICXPort0156]> { + let Latency = 3; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[ICXWriteResGroup48], (instrs CALL64pcrel32)>; + +def ICXWriteResGroup49 : SchedWriteRes<[ICXPort0]> { + let Latency = 4; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[ICXWriteResGroup49], (instregex "MUL_(FPrST0|FST0r|FrST0)")>; + +def ICXWriteResGroup50 : SchedWriteRes<[ICXPort01]> { + let Latency = 4; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[ICXWriteResGroup50], (instregex "VCVTDQ2PS(Y|Z128|Z256)rr", + "(V?)CVTDQ2PSrr", + "VCVTPD2QQ(Z128|Z256)rr", + "VCVTPD2UQQ(Z128|Z256)rr", + "VCVTPS2DQ(Y|Z128|Z256)rr", + "(V?)CVTPS2DQrr", + "VCVTPS2UDQ(Z128|Z256)rr", + "VCVTQQ2PD(Z128|Z256)rr", + "VCVTTPD2QQ(Z128|Z256)rr", + "VCVTTPD2UQQ(Z128|Z256)rr", + "VCVTTPS2DQ(Z128|Z256)rr", + "(V?)CVTTPS2DQrr", + "VCVTTPS2UDQ(Z128|Z256)rr", + "VCVTUDQ2PS(Z128|Z256)rr", + "VCVTUQQ2PD(Z128|Z256)rr")>; + +def ICXWriteResGroup50z : SchedWriteRes<[ICXPort05]> { + let Latency = 4; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[ICXWriteResGroup50z], (instrs VCVTDQ2PSZrr, + VCVTPD2QQZrr, + VCVTPD2UQQZrr, + VCVTPS2DQZrr, + VCVTPS2UDQZrr, + VCVTQQ2PDZrr, + VCVTTPD2QQZrr, + VCVTTPD2UQQZrr, + VCVTTPS2DQZrr, + VCVTTPS2UDQZrr, + VCVTUDQ2PSZrr, + VCVTUQQ2PDZrr)>; + +def ICXWriteResGroup51 : SchedWriteRes<[ICXPort5]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[ICXWriteResGroup51], (instregex "VEXPANDPD(Z|Z128|Z256)rr", + "VEXPANDPS(Z|Z128|Z256)rr", + "VPEXPANDD(Z|Z128|Z256)rr", + "VPEXPANDQ(Z|Z128|Z256)rr", + "VPMOVDB(Z|Z128|Z256)rr", + "VPMOVDW(Z|Z128|Z256)rr", + "VPMOVQB(Z|Z128|Z256)rr", + "VPMOVQW(Z|Z128|Z256)rr", + "VPMOVSDB(Z|Z128|Z256)rr", + "VPMOVSDW(Z|Z128|Z256)rr", + "VPMOVSQB(Z|Z128|Z256)rr", + "VPMOVSQD(Z|Z128|Z256)rr", + "VPMOVSQW(Z|Z128|Z256)rr", + "VPMOVSWB(Z|Z128|Z256)rr", + "VPMOVUSDB(Z|Z128|Z256)rr", + "VPMOVUSDW(Z|Z128|Z256)rr", + "VPMOVUSQB(Z|Z128|Z256)rr", + "VPMOVUSQD(Z|Z128|Z256)rr", + "VPMOVUSWB(Z|Z128|Z256)rr", + "VPMOVWB(Z|Z128|Z256)rr")>; + +def ICXWriteResGroup54 : SchedWriteRes<[ICXPort4,ICXPort5,ICXPort237]> { + let Latency = 4; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[ICXWriteResGroup54], (instregex "IST(T?)_FP(16|32|64)m", + "IST_F(16|32)m", + "VPMOVQD(Z|Z128|Z256)mr(b?)")>; + +def ICXWriteResGroup55 : SchedWriteRes<[ICXPort0156]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [4]; +} +def: InstRW<[ICXWriteResGroup55], (instrs FNCLEX)>; + +def ICXWriteResGroup56 : SchedWriteRes<[]> { + let Latency = 0; + let NumMicroOps = 4; + let ResourceCycles = []; +} +def: InstRW<[ICXWriteResGroup56], (instrs VZEROUPPER)>; + +def ICXWriteResGroup57 : SchedWriteRes<[ICXPort1,ICXPort6,ICXPort0156]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [1,1,2]; +} +def: InstRW<[ICXWriteResGroup57], (instregex "LAR(16|32|64)rr")>; + +def ICXWriteResGroup58 : SchedWriteRes<[ICXPort23]> { + let Latency = 5; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[ICXWriteResGroup58], (instregex "MOVSX(16|32|64)rm(8|16|32)", + "MOVZX(16|32|64)rm(8|16)", + "(V?)MOVDDUPrm")>; // TODO: Should this be ICXWriteResGroup71? + +def ICXWriteResGroup61 : SchedWriteRes<[ICXPort5,ICXPort015]> { + let Latency = 5; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[ICXWriteResGroup61], (instregex "MMX_CVT(T?)PD2PIirr", + "MMX_CVT(T?)PS2PIirr", + "VCVTDQ2PDZ128rr", + "VCVTPD2DQZ128rr", + "(V?)CVT(T?)PD2DQrr", + "VCVTPD2PSZ128rr", + "(V?)CVTPD2PSrr", + "VCVTPD2UDQZ128rr", + "VCVTPS2PDZ128rr", + "(V?)CVTPS2PDrr", + "VCVTPS2QQZ128rr", + "VCVTPS2UQQZ128rr", + "VCVTQQ2PSZ128rr", + "(V?)CVTSD2SS(Z?)rr", + "(V?)CVTSI(64)?2SDrr", + "VCVTSI2SSZrr", + "(V?)CVTSI2SSrr", + "VCVTSI(64)?2SDZrr", + "VCVTSS2SDZrr", + "(V?)CVTSS2SDrr", + "VCVTTPD2DQZ128rr", + "VCVTTPD2UDQZ128rr", + "VCVTTPS2QQZ128rr", + "VCVTTPS2UQQZ128rr", + "VCVTUDQ2PDZ128rr", + "VCVTUQQ2PSZ128rr", + "VCVTUSI2SSZrr", + "VCVTUSI(64)?2SDZrr")>; + +def ICXWriteResGroup62 : SchedWriteRes<[ICXPort5,ICXPort015]> { + let Latency = 5; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[ICXWriteResGroup62], (instregex "VPCONFLICTQZ128rr")>; + +def ICXWriteResGroup63 : SchedWriteRes<[ICXPort1,ICXPort6,ICXPort06]> { + let Latency = 5; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[ICXWriteResGroup63], (instregex "STR(16|32|64)r")>; + +def ICXWriteResGroup65 : SchedWriteRes<[ICXPort4,ICXPort237,ICXPort015]> { + let Latency = 5; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[ICXWriteResGroup65], (instregex "VCVTPS2PHZ128mr(b?)", + "VCVTPS2PHZ256mr(b?)", + "VCVTPS2PHZmr(b?)")>; + +def ICXWriteResGroup66 : SchedWriteRes<[ICXPort4,ICXPort5,ICXPort237]> { + let Latency = 5; + let NumMicroOps = 4; + let ResourceCycles = [1,2,1]; +} +def: InstRW<[ICXWriteResGroup66], (instregex "VPMOVDB(Z|Z128|Z256)mr(b?)", + "VPMOVDW(Z|Z128|Z256)mr(b?)", + "VPMOVQB(Z|Z128|Z256)mr(b?)", + "VPMOVQW(Z|Z128|Z256)mr(b?)", + "VPMOVSDB(Z|Z128|Z256)mr(b?)", + "VPMOVSDW(Z|Z128|Z256)mr(b?)", + "VPMOVSQB(Z|Z128|Z256)mr(b?)", + "VPMOVSQD(Z|Z128|Z256)mr(b?)", + "VPMOVSQW(Z|Z128|Z256)mr(b?)", + "VPMOVSWB(Z|Z128|Z256)mr(b?)", + "VPMOVUSDB(Z|Z128|Z256)mr(b?)", + "VPMOVUSDW(Z|Z128|Z256)mr(b?)", + "VPMOVUSQB(Z|Z128|Z256)mr(b?)", + "VPMOVUSQD(Z|Z128|Z256)mr(b?)", + "VPMOVUSQW(Z|Z128|Z256)mr(b?)", + "VPMOVUSWB(Z|Z128|Z256)mr(b?)", + "VPMOVWB(Z|Z128|Z256)mr(b?)")>; + +def ICXWriteResGroup67 : SchedWriteRes<[ICXPort06,ICXPort0156]> { + let Latency = 5; + let NumMicroOps = 5; + let ResourceCycles = [1,4]; +} +def: InstRW<[ICXWriteResGroup67], (instrs XSETBV)>; + +def ICXWriteResGroup69 : SchedWriteRes<[ICXPort4,ICXPort237,ICXPort0156]> { + let Latency = 5; + let NumMicroOps = 6; + let ResourceCycles = [1,1,4]; +} +def: InstRW<[ICXWriteResGroup69], (instregex "PUSHF(16|64)")>; + +def ICXWriteResGroup71 : SchedWriteRes<[ICXPort23]> { + let Latency = 6; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[ICXWriteResGroup71], (instrs VBROADCASTSSrm, + VPBROADCASTDrm, + VPBROADCASTQrm, + VMOVSHDUPrm, + VMOVSLDUPrm, + MOVSHDUPrm, + MOVSLDUPrm)>; + +def ICXWriteResGroup72 : SchedWriteRes<[ICXPort5]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[ICXWriteResGroup72], (instrs MMX_CVTPI2PSirr)>; +def: InstRW<[ICXWriteResGroup72], (instregex "VCOMPRESSPD(Z|Z128|Z256)rr", + "VCOMPRESSPS(Z|Z128|Z256)rr", + "VPCOMPRESSD(Z|Z128|Z256)rr", + "VPCOMPRESSQ(Z|Z128|Z256)rr", + "VPERMW(Z|Z128|Z256)rr")>; + +def ICXWriteResGroup73 : SchedWriteRes<[ICXPort0,ICXPort23]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[ICXWriteResGroup73], (instrs MMX_PADDSBirm, + MMX_PADDSWirm, + MMX_PADDUSBirm, + MMX_PADDUSWirm, + MMX_PAVGBirm, + MMX_PAVGWirm, + MMX_PCMPEQBirm, + MMX_PCMPEQDirm, + MMX_PCMPEQWirm, + MMX_PCMPGTBirm, + MMX_PCMPGTDirm, + MMX_PCMPGTWirm, + MMX_PMAXSWirm, + MMX_PMAXUBirm, + MMX_PMINSWirm, + MMX_PMINUBirm, + MMX_PSUBSBirm, + MMX_PSUBSWirm, + MMX_PSUBUSBirm, + MMX_PSUBUSWirm)>; + +def ICXWriteResGroup76 : SchedWriteRes<[ICXPort6,ICXPort23]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[ICXWriteResGroup76], (instrs FARJMP64m)>; +def: InstRW<[ICXWriteResGroup76], (instregex "JMP(16|32|64)m")>; + +def ICXWriteResGroup79 : SchedWriteRes<[ICXPort23,ICXPort15]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[ICXWriteResGroup79], (instregex "ANDN(32|64)rm", + "MOVBE(16|32|64)rm")>; + +def ICXWriteResGroup80 : SchedWriteRes<[ICXPort23,ICXPort015]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[ICXWriteResGroup80], (instregex "VMOV(64to|QI2)PQIZrm(b?)")>; +def: InstRW<[ICXWriteResGroup80], (instrs VMOVDI2PDIZrm)>; + +def ICXWriteResGroup81 : SchedWriteRes<[ICXPort23,ICXPort0156]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[ICXWriteResGroup81], (instrs POP16r, POP32r, POP64r)>; +def: InstRW<[ICXWriteResGroup81], (instregex "POP(16|32|64)rmr")>; + +def ICXWriteResGroup82 : SchedWriteRes<[ICXPort5,ICXPort015]> { + let Latency = 6; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[ICXWriteResGroup82], (instregex "(V?)CVTSI642SSrr", + "VCVTSI642SSZrr", + "VCVTUSI642SSZrr")>; + +def ICXWriteResGroup84 : SchedWriteRes<[ICXPort1,ICXPort6,ICXPort06,ICXPort0156]> { + let Latency = 6; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[ICXWriteResGroup84], (instregex "SLDT(16|32|64)r")>; + +def ICXWriteResGroup86 : SchedWriteRes<[ICXPort4,ICXPort23,ICXPort237,ICXPort06]> { + let Latency = 6; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[ICXWriteResGroup86], (instregex "SAR(8|16|32|64)m(1|i)", + "SHL(8|16|32|64)m(1|i)", + "SHR(8|16|32|64)m(1|i)")>; + +def ICXWriteResGroup87 : SchedWriteRes<[ICXPort4,ICXPort23,ICXPort237,ICXPort0156]> { + let Latency = 6; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[ICXWriteResGroup87], (instregex "POP(16|32|64)rmm", + "PUSH(16|32|64)rmm")>; + +def ICXWriteResGroup88 : SchedWriteRes<[ICXPort6,ICXPort0156]> { + let Latency = 6; + let NumMicroOps = 6; + let ResourceCycles = [1,5]; +} +def: InstRW<[ICXWriteResGroup88], (instrs STD)>; + +def ICXWriteResGroup89 : SchedWriteRes<[ICXPort23]> { + let Latency = 7; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[ICXWriteResGroup89], (instregex "LD_F(32|64|80)m")>; +def: InstRW<[ICXWriteResGroup89], (instrs VBROADCASTF128, + VBROADCASTI128, + VBROADCASTSDYrm, + VBROADCASTSSYrm, + VMOVDDUPYrm, + VMOVSHDUPYrm, + VMOVSLDUPYrm, + VPBROADCASTDYrm, + VPBROADCASTQYrm)>; + +def ICXWriteResGroup90 : SchedWriteRes<[ICXPort01,ICXPort5]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[ICXWriteResGroup90], (instrs VCVTDQ2PDYrr)>; + +def ICXWriteResGroup92 : SchedWriteRes<[ICXPort5,ICXPort23]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[ICXWriteResGroup92], (instregex "VMOVSDZrm(b?)", + "VMOVSSZrm(b?)")>; + +def ICXWriteResGroup92a : SchedWriteRes<[ICXPort5,ICXPort23]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[ICXWriteResGroup92a], (instregex "(V?)PMOV(SX|ZX)BDrm", + "(V?)PMOV(SX|ZX)BQrm", + "(V?)PMOV(SX|ZX)BWrm", + "(V?)PMOV(SX|ZX)DQrm", + "(V?)PMOV(SX|ZX)WDrm", + "(V?)PMOV(SX|ZX)WQrm")>; + +def ICXWriteResGroup93 : SchedWriteRes<[ICXPort5,ICXPort015]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[ICXWriteResGroup93], (instregex "VCVTDQ2PDZ256rr", + "VCVTPD2DQ(Y|Z256)rr", + "VCVTPD2PS(Y|Z256)rr", + "VCVTPD2UDQZ256rr", + "VCVTPS2PD(Y|Z256)rr", + "VCVTPS2QQZ256rr", + "VCVTPS2UQQZ256rr", + "VCVTQQ2PSZ256rr", + "VCVTTPD2DQ(Y|Z256)rr", + "VCVTTPD2UDQZ256rr", + "VCVTTPS2QQZ256rr", + "VCVTTPS2UQQZ256rr", + "VCVTUDQ2PDZ256rr", + "VCVTUQQ2PSZ256rr")>; + +def ICXWriteResGroup93z : SchedWriteRes<[ICXPort5,ICXPort05]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[ICXWriteResGroup93z], (instrs VCVTDQ2PDZrr, + VCVTPD2DQZrr, + VCVTPD2PSZrr, + VCVTPD2UDQZrr, + VCVTPS2PDZrr, + VCVTPS2QQZrr, + VCVTPS2UQQZrr, + VCVTQQ2PSZrr, + VCVTTPD2DQZrr, + VCVTTPD2UDQZrr, + VCVTTPS2QQZrr, + VCVTTPS2UQQZrr, + VCVTUDQ2PDZrr, + VCVTUQQ2PSZrr)>; + +def ICXWriteResGroup95 : SchedWriteRes<[ICXPort23,ICXPort015]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[ICXWriteResGroup95], (instrs VMOVNTDQAZ128rm, + VPBLENDDrmi)>; +def: InstRW<[ICXWriteResGroup95, ReadAfterVecXLd], + (instregex "VBLENDMPDZ128rm(b?)", + "VBLENDMPSZ128rm(b?)", + "VBROADCASTI32X2Z128rm(b?)", + "VBROADCASTSSZ128rm(b?)", + "VINSERT(F|I)128rm", + "VMOVAPDZ128rm(b?)", + "VMOVAPSZ128rm(b?)", + "VMOVDDUPZ128rm(b?)", + "VMOVDQA32Z128rm(b?)", + "VMOVDQA64Z128rm(b?)", + "VMOVDQU16Z128rm(b?)", + "VMOVDQU32Z128rm(b?)", + "VMOVDQU64Z128rm(b?)", + "VMOVDQU8Z128rm(b?)", + "VMOVSHDUPZ128rm(b?)", + "VMOVSLDUPZ128rm(b?)", + "VMOVUPDZ128rm(b?)", + "VMOVUPSZ128rm(b?)", + "VPADD(B|D|Q|W)Z128rm(b?)", + "(V?)PADD(B|D|Q|W)rm", + "VPBLENDM(B|D|Q|W)Z128rm(b?)", + "VPBROADCASTDZ128rm(b?)", + "VPBROADCASTQZ128rm(b?)", + "VPSUB(B|D|Q|W)Z128rm(b?)", + "(V?)PSUB(B|D|Q|W)rm", + "VPTERNLOGDZ128rm(b?)i", + "VPTERNLOGQZ128rm(b?)i")>; + +def ICXWriteResGroup96 : SchedWriteRes<[ICXPort5,ICXPort23]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[ICXWriteResGroup96], (instrs MMX_PACKSSDWirm, + MMX_PACKSSWBirm, + MMX_PACKUSWBirm)>; + +def ICXWriteResGroup97 : SchedWriteRes<[ICXPort5,ICXPort015]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[ICXWriteResGroup97], (instregex "VPERMI2W128rr", + "VPERMI2W256rr", + "VPERMI2Wrr", + "VPERMT2W128rr", + "VPERMT2W256rr", + "VPERMT2Wrr")>; + +def ICXWriteResGroup99 : SchedWriteRes<[ICXPort23,ICXPort0156]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[ICXWriteResGroup99], (instrs LEAVE, LEAVE64, + SCASB, SCASL, SCASQ, SCASW)>; + +def ICXWriteResGroup100 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort015]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[ICXWriteResGroup100], (instregex "VCVTSS2USI64Zrr", + "(V?)CVTSS2SI64(Z?)rr", + "(V?)CVTTSS2SI64(Z?)rr", + "VCVTTSS2USI64Zrr")>; + +def ICXWriteResGroup101 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort05]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[ICXWriteResGroup101], (instrs FLDCW16m)>; + +def ICXWriteResGroup103 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort0156]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[ICXWriteResGroup103], (instregex "KMOV(B|D|Q|W)km")>; + +def ICXWriteResGroup104 : SchedWriteRes<[ICXPort6,ICXPort23,ICXPort0156]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[ICXWriteResGroup104], (instrs LRETQ, RETQ)>; + +def ICXWriteResGroup106 : SchedWriteRes<[ICXPort4,ICXPort5,ICXPort237]> { + let Latency = 7; + let NumMicroOps = 4; + let ResourceCycles = [1,2,1]; +} +def: InstRW<[ICXWriteResGroup106], (instregex "VCOMPRESSPD(Z|Z128|Z256)mr(b?)", + "VCOMPRESSPS(Z|Z128|Z256)mr(b?)", + "VPCOMPRESSD(Z|Z128|Z256)mr(b?)", + "VPCOMPRESSQ(Z|Z128|Z256)mr(b?)")>; + +def ICXWriteResGroup107 : SchedWriteRes<[ICXPort4,ICXPort23,ICXPort237,ICXPort06]> { + let Latency = 7; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,2]; +} +def: InstRW<[ICXWriteResGroup107], (instregex "ROL(8|16|32|64)m(1|i)", + "ROR(8|16|32|64)m(1|i)")>; + +def ICXWriteResGroup107_1 : SchedWriteRes<[ICXPort06]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[ICXWriteResGroup107_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1, + ROR8r1, ROR16r1, ROR32r1, ROR64r1)>; + +def ICXWriteResGroup108 : SchedWriteRes<[ICXPort4,ICXPort23,ICXPort237,ICXPort0156]> { + let Latency = 7; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,2]; +} +def: InstRW<[ICXWriteResGroup108], (instregex "XADD(8|16|32|64)rm")>; + +def ICXWriteResGroup109 : SchedWriteRes<[ICXPort4,ICXPort6,ICXPort23,ICXPort237,ICXPort0156]> { + let Latency = 7; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,1,1]; +} +def: InstRW<[ICXWriteResGroup109], (instregex "CALL(16|32|64)m")>; +def: InstRW<[ICXWriteResGroup109], (instrs FARCALL64m)>; + +def ICXWriteResGroup110 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort237,ICXPort0156]> { + let Latency = 7; + let NumMicroOps = 7; + let ResourceCycles = [1,2,2,2]; +} +def: InstRW<[ICXWriteResGroup110], (instrs VPSCATTERDQZ128mr, + VPSCATTERQQZ128mr, + VSCATTERDPDZ128mr, + VSCATTERQPDZ128mr)>; + +def ICXWriteResGroup111 : SchedWriteRes<[ICXPort6,ICXPort06,ICXPort15,ICXPort0156]> { + let Latency = 7; + let NumMicroOps = 7; + let ResourceCycles = [1,3,1,2]; +} +def: InstRW<[ICXWriteResGroup111], (instrs LOOP)>; + +def ICXWriteResGroup112 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort237,ICXPort0156]> { + let Latency = 7; + let NumMicroOps = 11; + let ResourceCycles = [1,4,4,2]; +} +def: InstRW<[ICXWriteResGroup112], (instrs VPSCATTERDQZ256mr, + VPSCATTERQQZ256mr, + VSCATTERDPDZ256mr, + VSCATTERQPDZ256mr)>; + +def ICXWriteResGroup113 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort237,ICXPort0156]> { + let Latency = 7; + let NumMicroOps = 19; + let ResourceCycles = [1,8,8,2]; +} +def: InstRW<[ICXWriteResGroup113], (instrs VPSCATTERDQZmr, + VPSCATTERQQZmr, + VSCATTERDPDZmr, + VSCATTERQPDZmr)>; + +def ICXWriteResGroup114 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort5,ICXPort237,ICXPort0156]> { + let Latency = 7; + let NumMicroOps = 36; + let ResourceCycles = [1,16,1,16,2]; +} +def: InstRW<[ICXWriteResGroup114], (instrs VSCATTERDPSZmr)>; + +def ICXWriteResGroup118 : SchedWriteRes<[ICXPort1,ICXPort23]> { + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[ICXWriteResGroup118], (instregex "PDEP(32|64)rm", + "PEXT(32|64)rm")>; + +def ICXWriteResGroup119 : SchedWriteRes<[ICXPort5,ICXPort23]> { + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[ICXWriteResGroup119], (instregex "FCOM(P?)(32|64)m", + "VPBROADCASTB(Z|Z256)rm(b?)", + "VPBROADCASTW(Z|Z256)rm(b?)")>; +def: InstRW<[ICXWriteResGroup119], (instrs VPBROADCASTBYrm, + VPBROADCASTWYrm, + VPMOVSXBDYrm, + VPMOVSXBQYrm, + VPMOVSXWQYrm)>; + +def ICXWriteResGroup121 : SchedWriteRes<[ICXPort23,ICXPort015]> { + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[ICXWriteResGroup121], (instrs VMOVNTDQAZ256rm, + VPBLENDDYrmi)>; +def: InstRW<[ICXWriteResGroup121, ReadAfterVecYLd], + (instregex "VBLENDMPD(Z|Z256)rm(b?)", + "VBLENDMPS(Z|Z256)rm(b?)", + "VBROADCASTF32X2Z256rm(b?)", + "VBROADCASTF32X2Zrm(b?)", + "VBROADCASTF32X4Z256rm(b?)", + "VBROADCASTF32X4rm(b?)", + "VBROADCASTF32X8rm(b?)", + "VBROADCASTF64X2Z128rm(b?)", + "VBROADCASTF64X2rm(b?)", + "VBROADCASTF64X4rm(b?)", + "VBROADCASTI32X2Z256rm(b?)", + "VBROADCASTI32X2Zrm(b?)", + "VBROADCASTI32X4Z256rm(b?)", + "VBROADCASTI32X4rm(b?)", + "VBROADCASTI32X8rm(b?)", + "VBROADCASTI64X2Z128rm(b?)", + "VBROADCASTI64X2rm(b?)", + "VBROADCASTI64X4rm(b?)", + "VBROADCASTSD(Z|Z256)rm(b?)", + "VBROADCASTSS(Z|Z256)rm(b?)", + "VINSERTF32x4(Z|Z256)rm(b?)", + "VINSERTF32x8Zrm(b?)", + "VINSERTF64x2(Z|Z256)rm(b?)", + "VINSERTF64x4Zrm(b?)", + "VINSERTI32x4(Z|Z256)rm(b?)", + "VINSERTI32x8Zrm(b?)", + "VINSERTI64x2(Z|Z256)rm(b?)", + "VINSERTI64x4Zrm(b?)", + "VMOVAPD(Z|Z256)rm(b?)", + "VMOVAPS(Z|Z256)rm(b?)", + "VMOVDDUP(Z|Z256)rm(b?)", + "VMOVDQA32(Z|Z256)rm(b?)", + "VMOVDQA64(Z|Z256)rm(b?)", + "VMOVDQU16(Z|Z256)rm(b?)", + "VMOVDQU32(Z|Z256)rm(b?)", + "VMOVDQU64(Z|Z256)rm(b?)", + "VMOVDQU8(Z|Z256)rm(b?)", + "VMOVSHDUP(Z|Z256)rm(b?)", + "VMOVSLDUP(Z|Z256)rm(b?)", + "VMOVUPD(Z|Z256)rm(b?)", + "VMOVUPS(Z|Z256)rm(b?)", + "VPADD(B|D|Q|W)Yrm", + "VPADD(B|D|Q|W)(Z|Z256)rm(b?)", + "VPBLENDM(B|D|Q|W)(Z|Z256)rm(b?)", + "VPBROADCASTD(Z|Z256)rm(b?)", + "VPBROADCASTQ(Z|Z256)rm(b?)", + "VPSUB(B|D|Q|W)Yrm", + "VPSUB(B|D|Q|W)(Z|Z256)rm(b?)", + "VPTERNLOGD(Z|Z256)rm(b?)i", + "VPTERNLOGQ(Z|Z256)rm(b?)i")>; + +def ICXWriteResGroup123 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> { + let Latency = 8; + let NumMicroOps = 4; + let ResourceCycles = [1,2,1]; +} +def: InstRW<[ICXWriteResGroup123], (instregex "MMX_PH(ADD|SUB)SWrm")>; + +def ICXWriteResGroup127 : SchedWriteRes<[ICXPort23,ICXPort237,ICXPort06,ICXPort0156]> { + let Latency = 8; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,2]; +} +def: InstRW<[ICXWriteResGroup127], (instregex "RCL(8|16|32|64)m(1|i)", + "RCR(8|16|32|64)m(1|i)")>; + +def ICXWriteResGroup128 : SchedWriteRes<[ICXPort4,ICXPort23,ICXPort237,ICXPort06]> { + let Latency = 8; + let NumMicroOps = 6; + let ResourceCycles = [1,1,1,3]; +} +def: InstRW<[ICXWriteResGroup128], (instregex "ROL(8|16|32|64)mCL", + "ROR(8|16|32|64)mCL", + "SAR(8|16|32|64)mCL", + "SHL(8|16|32|64)mCL", + "SHR(8|16|32|64)mCL")>; + +def ICXWriteResGroup130 : SchedWriteRes<[ICXPort4,ICXPort23,ICXPort237,ICXPort06,ICXPort0156]> { + let Latency = 8; + let NumMicroOps = 6; + let ResourceCycles = [1,1,1,2,1]; +} +def: SchedAlias; + +def ICXWriteResGroup131 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort5,ICXPort237,ICXPort0156]> { + let Latency = 8; + let NumMicroOps = 8; + let ResourceCycles = [1,2,1,2,2]; +} +def: InstRW<[ICXWriteResGroup131], (instrs VPSCATTERQDZ128mr, + VPSCATTERQDZ256mr, + VSCATTERQPSZ128mr, + VSCATTERQPSZ256mr)>; + +def ICXWriteResGroup132 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort5,ICXPort237,ICXPort0156]> { + let Latency = 8; + let NumMicroOps = 12; + let ResourceCycles = [1,4,1,4,2]; +} +def: InstRW<[ICXWriteResGroup132], (instrs VPSCATTERDDZ128mr, + VSCATTERDPSZ128mr)>; + +def ICXWriteResGroup133 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort5,ICXPort237,ICXPort0156]> { + let Latency = 8; + let NumMicroOps = 20; + let ResourceCycles = [1,8,1,8,2]; +} +def: InstRW<[ICXWriteResGroup133], (instrs VPSCATTERDDZ256mr, + VSCATTERDPSZ256mr)>; + +def ICXWriteResGroup134 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort5,ICXPort237,ICXPort0156]> { + let Latency = 8; + let NumMicroOps = 36; + let ResourceCycles = [1,16,1,16,2]; +} +def: InstRW<[ICXWriteResGroup134], (instrs VPSCATTERDDZmr)>; + +def ICXWriteResGroup135 : SchedWriteRes<[ICXPort0,ICXPort23]> { + let Latency = 9; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[ICXWriteResGroup135], (instrs MMX_CVTPI2PSirm)>; + +def ICXWriteResGroup136 : SchedWriteRes<[ICXPort5,ICXPort23]> { + let Latency = 9; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[ICXWriteResGroup136], (instrs VPMOVSXBWYrm, + VPMOVSXDQYrm, + VPMOVSXWDYrm, + VPMOVZXWDYrm)>; +def: InstRW<[ICXWriteResGroup136], (instregex "VALIGN(D|Q)Z128rm(b?)i", + "VFPCLASSSDZrm(b?)", + "VFPCLASSSSZrm(b?)", + "(V?)PCMPGTQrm", + "VPERMI2D128rm(b?)", + "VPERMI2PD128rm(b?)", + "VPERMI2PS128rm(b?)", + "VPERMI2Q128rm(b?)", + "VPERMT2D128rm(b?)", + "VPERMT2PD128rm(b?)", + "VPERMT2PS128rm(b?)", + "VPERMT2Q128rm(b?)", + "VPMAXSQZ128rm(b?)", + "VPMAXUQZ128rm(b?)", + "VPMINSQZ128rm(b?)", + "VPMINUQZ128rm(b?)", + "VPMOVSXBDZ128rm(b?)", + "VPMOVSXBQZ128rm(b?)", + "VPMOVSXBWZ128rm(b?)", + "VPMOVSXDQZ128rm(b?)", + "VPMOVSXWDZ128rm(b?)", + "VPMOVSXWQZ128rm(b?)", + "VPMOVZXBDZ128rm(b?)", + "VPMOVZXBQZ128rm(b?)", + "VPMOVZXBWZ128rm(b?)", + "VPMOVZXDQZ128rm(b?)", + "VPMOVZXWDZ128rm(b?)", + "VPMOVZXWQZ128rm(b?)")>; + +def ICXWriteResGroup136_2 : SchedWriteRes<[ICXPort5,ICXPort23]> { + let Latency = 10; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[ICXWriteResGroup136_2], (instregex "VCMP(PD|PS)Z128rm(b?)i", + "VCMP(SD|SS)Zrm", + "VFPCLASSPDZ128rm(b?)", + "VFPCLASSPSZ128rm(b?)", + "VPCMPBZ128rmi(b?)", + "VPCMPDZ128rmi(b?)", + "VPCMPEQ(B|D|Q|W)Z128rm(b?)", + "VPCMPGT(B|D|Q|W)Z128rm(b?)", + "VPCMPQZ128rmi(b?)", + "VPCMPU(B|D|Q|W)Z128rmi(b?)", + "VPCMPWZ128rmi(b?)", + "VPTESTMBZ128rm(b?)", + "VPTESTMDZ128rm(b?)", + "VPTESTMQZ128rm(b?)", + "VPTESTMWZ128rm(b?)", + "VPTESTNMBZ128rm(b?)", + "VPTESTNMDZ128rm(b?)", + "VPTESTNMQZ128rm(b?)", + "VPTESTNMWZ128rm(b?)")>; + +def ICXWriteResGroup137 : SchedWriteRes<[ICXPort23,ICXPort015]> { + let Latency = 9; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[ICXWriteResGroup137], (instregex "MMX_CVT(T?)PS2PIirm", + "(V?)CVTPS2PDrm")>; + +def ICXWriteResGroup143 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort23]> { + let Latency = 9; + let NumMicroOps = 4; + let ResourceCycles = [2,1,1]; +} +def: InstRW<[ICXWriteResGroup143], (instregex "(V?)PHADDSWrm", + "(V?)PHSUBSWrm")>; + +def ICXWriteResGroup146 : SchedWriteRes<[ICXPort1,ICXPort6,ICXPort23,ICXPort0156]> { + let Latency = 9; + let NumMicroOps = 5; + let ResourceCycles = [1,2,1,1]; +} +def: InstRW<[ICXWriteResGroup146], (instregex "LAR(16|32|64)rm", + "LSL(16|32|64)rm")>; + +def ICXWriteResGroup148 : SchedWriteRes<[ICXPort5,ICXPort23]> { + let Latency = 10; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[ICXWriteResGroup148], (instrs VPCMPGTQYrm)>; +def: InstRW<[ICXWriteResGroup148], (instregex "(ADD|SUB|SUBR)_F(32|64)m", + "ILD_F(16|32|64)m", + "VALIGND(Z|Z256)rm(b?)i", + "VALIGNQ(Z|Z256)rm(b?)i", + "VPMAXSQ(Z|Z256)rm(b?)", + "VPMAXUQ(Z|Z256)rm(b?)", + "VPMINSQ(Z|Z256)rm(b?)", + "VPMINUQ(Z|Z256)rm(b?)")>; + +def ICXWriteResGroup148_2 : SchedWriteRes<[ICXPort5,ICXPort23]> { + let Latency = 11; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[ICXWriteResGroup148_2], (instregex "VCMPPD(Z|Z256)rm(b?)i", + "VCMPPS(Z|Z256)rm(b?)i", + "VFPCLASSPD(Z|Z256)rm(b?)", + "VFPCLASSPS(Z|Z256)rm(b?)", + "VPCMPB(Z|Z256)rmi(b?)", + "VPCMPD(Z|Z256)rmi(b?)", + "VPCMPEQB(Z|Z256)rm(b?)", + "VPCMPEQD(Z|Z256)rm(b?)", + "VPCMPEQQ(Z|Z256)rm(b?)", + "VPCMPEQW(Z|Z256)rm(b?)", + "VPCMPGTB(Z|Z256)rm(b?)", + "VPCMPGTD(Z|Z256)rm(b?)", + "VPCMPGTQ(Z|Z256)rm(b?)", + "VPCMPGTW(Z|Z256)rm(b?)", + "VPCMPQ(Z|Z256)rmi(b?)", + "VPCMPU(B|D|Q|W)Z256rmi(b?)", + "VPCMPU(B|D|Q|W)Zrmi(b?)", + "VPCMPW(Z|Z256)rmi(b?)", + "VPTESTM(B|D|Q|W)Z256rm(b?)", + "VPTESTM(B|D|Q|W)Zrm(b?)", + "VPTESTNM(B|D|Q|W)Z256rm(b?)", + "VPTESTNM(B|D|Q|W)Zrm(b?)")>; + +def ICXWriteResGroup149 : SchedWriteRes<[ICXPort23,ICXPort015]> { + let Latency = 10; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[ICXWriteResGroup149], (instregex "VCVTDQ2PDZ128rm(b?)", + "VCVTDQ2PSZ128rm(b?)", + "(V?)CVTDQ2PSrm", + "VCVTPD2QQZ128rm(b?)", + "VCVTPD2UQQZ128rm(b?)", + "VCVTPH2PSZ128rm(b?)", + "VCVTPS2DQZ128rm(b?)", + "(V?)CVTPS2DQrm", + "VCVTPS2PDZ128rm(b?)", + "VCVTPS2QQZ128rm(b?)", + "VCVTPS2UDQZ128rm(b?)", + "VCVTPS2UQQZ128rm(b?)", + "VCVTQQ2PDZ128rm(b?)", + "VCVTQQ2PSZ128rm(b?)", + "VCVTSS2SDZrm", + "(V?)CVTSS2SDrm", + "VCVTTPD2QQZ128rm(b?)", + "VCVTTPD2UQQZ128rm(b?)", + "VCVTTPS2DQZ128rm(b?)", + "(V?)CVTTPS2DQrm", + "VCVTTPS2QQZ128rm(b?)", + "VCVTTPS2UDQZ128rm(b?)", + "VCVTTPS2UQQZ128rm(b?)", + "VCVTUDQ2PDZ128rm(b?)", + "VCVTUDQ2PSZ128rm(b?)", + "VCVTUQQ2PDZ128rm(b?)", + "VCVTUQQ2PSZ128rm(b?)")>; + +def ICXWriteResGroup151 : SchedWriteRes<[ICXPort5,ICXPort23]> { + let Latency = 10; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[ICXWriteResGroup151], (instregex "VEXPANDPDZ128rm(b?)", + "VEXPANDPSZ128rm(b?)", + "VPEXPANDDZ128rm(b?)", + "VPEXPANDQZ128rm(b?)")>; + +def ICXWriteResGroup153 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> { + let Latency = 10; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[ICXWriteResGroup153], (instregex "(V?)CVTSD2SSrm")>; + +def ICXWriteResGroup154 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort23]> { + let Latency = 10; + let NumMicroOps = 4; + let ResourceCycles = [2,1,1]; +} +def: InstRW<[ICXWriteResGroup154], (instrs VPHADDSWYrm, + VPHSUBSWYrm)>; + +def ICXWriteResGroup157 : SchedWriteRes<[ICXPort4,ICXPort6,ICXPort23,ICXPort237,ICXPort06,ICXPort0156]> { + let Latency = 10; + let NumMicroOps = 8; + let ResourceCycles = [1,1,1,1,1,3]; +} +def: InstRW<[ICXWriteResGroup157], (instregex "XCHG(8|16|32|64)rm")>; + +def ICXWriteResGroup159 : SchedWriteRes<[ICXPort0,ICXFPDivider]> { + let Latency = 11; + let NumMicroOps = 1; + let ResourceCycles = [1,3]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def ICXWriteResGroup160 : SchedWriteRes<[ICXPort0,ICXPort23]> { + let Latency = 11; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[ICXWriteResGroup160], (instregex "MUL_F(32|64)m")>; + +def ICXWriteResGroup161 : SchedWriteRes<[ICXPort23,ICXPort015]> { + let Latency = 11; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[ICXWriteResGroup161], (instrs VCVTDQ2PSYrm, + VCVTPS2PDYrm)>; +def: InstRW<[ICXWriteResGroup161], (instregex "VCVTDQ2(PD|PS)(Z|Z256)rm(b?)", + "VCVTPH2PS(Z|Z256)rm(b?)", + "VCVTPS2PD(Z|Z256)rm(b?)", + "VCVTQQ2PD(Z|Z256)rm(b?)", + "VCVTQQ2PSZ256rm(b?)", + "VCVT(T?)PD2QQ(Z|Z256)rm(b?)", + "VCVT(T?)PD2UQQ(Z|Z256)rm(b?)", + "VCVT(T?)PS2DQYrm", + "VCVT(T?)PS2DQ(Z|Z256)rm(b?)", + "VCVT(T?)PS2QQZ256rm(b?)", + "VCVT(T?)PS2UDQ(Z|Z256)rm(b?)", + "VCVT(T?)PS2UQQZ256rm(b?)", + "VCVTUDQ2(PD|PS)(Z|Z256)rm(b?)", + "VCVTUQQ2PD(Z|Z256)rm(b?)", + "VCVTUQQ2PSZ256rm(b?)")>; + +def ICXWriteResGroup162 : SchedWriteRes<[ICXPort5,ICXPort23]> { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[ICXWriteResGroup162], (instregex "FICOM(P?)(16|32)m", + "VEXPANDPD(Z|Z256)rm(b?)", + "VEXPANDPS(Z|Z256)rm(b?)", + "VPEXPANDD(Z|Z256)rm(b?)", + "VPEXPANDQ(Z|Z256)rm(b?)")>; + +def ICXWriteResGroup163 : SchedWriteRes<[ICXPort23,ICXPort015]> { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[ICXWriteResGroup163], (instregex "VCVTSD2SSZrm")>; + +def ICXWriteResGroup164 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[ICXWriteResGroup164], (instregex "(V?)CVTDQ2PDrm")>; + +def ICXWriteResGroup166 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[ICXWriteResGroup166], (instrs CVTPD2PSrm, + CVTPD2DQrm, + CVTTPD2DQrm, + MMX_CVTPD2PIirm, + MMX_CVTTPD2PIirm)>; + +def ICXWriteResGroup167 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> { + let Latency = 11; + let NumMicroOps = 4; + let ResourceCycles = [2,1,1]; +} +def: InstRW<[ICXWriteResGroup167], (instregex "VPCONFLICTQZ128rm(b?)")>; + +def ICXWriteResGroup169 : SchedWriteRes<[ICXPort1,ICXPort06,ICXPort0156]> { + let Latency = 11; + let NumMicroOps = 7; + let ResourceCycles = [2,3,2]; +} +def: InstRW<[ICXWriteResGroup169], (instregex "RCL(16|32|64)rCL", + "RCR(16|32|64)rCL")>; + +def ICXWriteResGroup170 : SchedWriteRes<[ICXPort1,ICXPort06,ICXPort15,ICXPort0156]> { + let Latency = 11; + let NumMicroOps = 9; + let ResourceCycles = [1,5,1,2]; +} +def: InstRW<[ICXWriteResGroup170], (instrs RCL8rCL)>; + +def ICXWriteResGroup171 : SchedWriteRes<[ICXPort06,ICXPort0156]> { + let Latency = 11; + let NumMicroOps = 11; + let ResourceCycles = [2,9]; +} +def: InstRW<[ICXWriteResGroup171], (instrs LOOPE, LOOPNE)>; + +def ICXWriteResGroup174 : SchedWriteRes<[ICXPort01]> { + let Latency = 15; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def: InstRW<[ICXWriteResGroup174], (instregex "VPMULLQ(Z128|Z256)rr")>; + +def ICXWriteResGroup174z : SchedWriteRes<[ICXPort05]> { + let Latency = 15; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def: InstRW<[ICXWriteResGroup174z], (instregex "VPMULLQZrr")>; + +def ICXWriteResGroup175 : SchedWriteRes<[ICXPort5,ICXPort23]> { + let Latency = 12; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[ICXWriteResGroup175], (instregex "VPERMWZ128rm(b?)")>; + +def ICXWriteResGroup176 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort015]> { + let Latency = 12; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[ICXWriteResGroup176], (instregex "VCVT(T?)SD2USIZrm(b?)", + "VCVT(T?)SS2USI64Zrm(b?)")>; + +def ICXWriteResGroup177 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> { + let Latency = 12; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[ICXWriteResGroup177], (instregex "VCVT(T?)PS2QQZrm(b?)", + "VCVT(T?)PS2UQQZrm(b?)")>; + +def ICXWriteResGroup179 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23,ICXPort015]> { + let Latency = 12; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[ICXWriteResGroup179], (instregex "CVTTSS2SI64rm")>; + +def ICXWriteResGroup180 : SchedWriteRes<[ICXPort5,ICXPort23]> { + let Latency = 13; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[ICXWriteResGroup180], (instregex "(ADD|SUB|SUBR)_FI(16|32)m", + "VPERMWZ256rm(b?)", + "VPERMWZrm(b?)")>; + +def ICXWriteResGroup181 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> { + let Latency = 13; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[ICXWriteResGroup181], (instrs VCVTDQ2PDYrm)>; + +def ICXWriteResGroup183 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> { + let Latency = 13; + let NumMicroOps = 4; + let ResourceCycles = [2,1,1]; +} +def: InstRW<[ICXWriteResGroup183], (instregex "VPERMI2W128rm(b?)", + "VPERMT2W128rm(b?)")>; + +def ICXWriteResGroup184 : SchedWriteRes<[ICXPort0,ICXFPDivider]> { + let Latency = 14; + let NumMicroOps = 1; + let ResourceCycles = [1,3]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def ICXWriteResGroup184_1 : SchedWriteRes<[ICXPort0,ICXFPDivider]> { + let Latency = 14; + let NumMicroOps = 1; + let ResourceCycles = [1,5]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def ICXWriteResGroup187 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> { + let Latency = 14; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[ICXWriteResGroup187], (instregex "MUL_FI(16|32)m")>; + +def ICXWriteResGroup188 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> { + let Latency = 14; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[ICXWriteResGroup188], (instregex "VCVTPD2DQZrm(b?)", + "VCVTPD2PSZrm(b?)", + "VCVTPD2UDQZrm(b?)", + "VCVTQQ2PSZrm(b?)", + "VCVTTPD2DQZrm(b?)", + "VCVTTPD2UDQZrm(b?)", + "VCVTUQQ2PSZrm(b?)")>; + +def ICXWriteResGroup189 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> { + let Latency = 14; + let NumMicroOps = 4; + let ResourceCycles = [2,1,1]; +} +def: InstRW<[ICXWriteResGroup189], (instregex "VPERMI2W256rm(b?)", + "VPERMI2Wrm(b?)", + "VPERMT2W256rm(b?)", + "VPERMT2Wrm(b?)")>; + +def ICXWriteResGroup190 : SchedWriteRes<[ICXPort1,ICXPort06,ICXPort15,ICXPort0156]> { + let Latency = 14; + let NumMicroOps = 10; + let ResourceCycles = [2,4,1,3]; +} +def: InstRW<[ICXWriteResGroup190], (instrs RCR8rCL)>; + +def ICXWriteResGroup191 : SchedWriteRes<[ICXPort0]> { + let Latency = 15; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[ICXWriteResGroup191], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>; + +def ICXWriteResGroup194 : SchedWriteRes<[ICXPort1,ICXPort5,ICXPort01,ICXPort23,ICXPort015]> { + let Latency = 15; + let NumMicroOps = 8; + let ResourceCycles = [1,2,2,1,2]; +} +def: InstRW<[ICXWriteResGroup194], (instregex "VPCONFLICTDZ128rm(b?)")>; + +def ICXWriteResGroup195 : SchedWriteRes<[ICXPort1,ICXPort23,ICXPort237,ICXPort06,ICXPort15,ICXPort0156]> { + let Latency = 15; + let NumMicroOps = 10; + let ResourceCycles = [1,1,1,5,1,1]; +} +def: InstRW<[ICXWriteResGroup195], (instregex "RCL(8|16|32|64)mCL")>; + +def ICXWriteResGroup199 : SchedWriteRes<[ICXPort4,ICXPort23,ICXPort237,ICXPort06,ICXPort15,ICXPort0156]> { + let Latency = 16; + let NumMicroOps = 14; + let ResourceCycles = [1,1,1,4,2,5]; +} +def: InstRW<[ICXWriteResGroup199], (instrs CMPXCHG8B)>; + +def ICXWriteResGroup200 : SchedWriteRes<[ICXPort1, ICXPort05, ICXPort6]> { + let Latency = 12; + let NumMicroOps = 34; + let ResourceCycles = [1, 4, 5]; +} +def: InstRW<[ICXWriteResGroup200], (instrs VZEROALL)>; + +def ICXWriteResGroup201 : SchedWriteRes<[ICXPort0,ICXPort23,ICXFPDivider]> { + let Latency = 17; + let NumMicroOps = 2; + let ResourceCycles = [1,1,5]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def ICXWriteResGroup202 : SchedWriteRes<[ICXPort0,ICXPort1,ICXPort5,ICXPort6,ICXPort05,ICXPort0156]> { + let Latency = 17; + let NumMicroOps = 15; + let ResourceCycles = [2,1,2,4,2,4]; +} +def: InstRW<[ICXWriteResGroup202], (instrs XCH_F)>; + +def ICXWriteResGroup205 : SchedWriteRes<[ICXPort23,ICXPort01]> { + let Latency = 21; + let NumMicroOps = 4; + let ResourceCycles = [1,3]; +} +def: InstRW<[ICXWriteResGroup205], (instregex "VPMULLQZ128rm(b?)")>; + +def ICXWriteResGroup207 : SchedWriteRes<[ICXPort5,ICXPort6,ICXPort06,ICXPort0156]> { + let Latency = 18; + let NumMicroOps = 8; + let ResourceCycles = [1,1,1,5]; +} +def: InstRW<[ICXWriteResGroup207], (instrs CPUID, RDTSC)>; + +def ICXWriteResGroup208 : SchedWriteRes<[ICXPort1,ICXPort23,ICXPort237,ICXPort06,ICXPort15,ICXPort0156]> { + let Latency = 18; + let NumMicroOps = 11; + let ResourceCycles = [2,1,1,4,1,2]; +} +def: InstRW<[ICXWriteResGroup208], (instregex "RCR(8|16|32|64)mCL")>; + +def ICXWriteResGroup209 : SchedWriteRes<[ICXPort0,ICXPort23,ICXFPDivider]> { + let Latency = 19; + let NumMicroOps = 2; + let ResourceCycles = [1,1,4]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def ICXWriteResGroup211 : SchedWriteRes<[ICXPort23,ICXPort01]> { + let Latency = 22; + let NumMicroOps = 4; + let ResourceCycles = [1,3]; +} +def: InstRW<[ICXWriteResGroup211], (instregex "VPMULLQZ256rm(b?)")>; + +def ICXWriteResGroup211_1 : SchedWriteRes<[ICXPort23,ICXPort05]> { + let Latency = 22; + let NumMicroOps = 4; + let ResourceCycles = [1,3]; +} +def: InstRW<[ICXWriteResGroup211_1], (instregex "VPMULLQZrm(b?)")>; + +def ICXWriteResGroup215 : SchedWriteRes<[ICXPort0]> { + let Latency = 20; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[ICXWriteResGroup215], (instregex "DIV_(FPrST0|FST0r|FrST0)")>; + +def ICXWriteResGroup216 : SchedWriteRes<[ICXPort0,ICXPort23,ICXFPDivider]> { + let Latency = 20; + let NumMicroOps = 2; + let ResourceCycles = [1,1,4]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def ICXWriteGatherEVEX2 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort015,ICXPort0156]> { + let Latency = 17; + let NumMicroOps = 5; // 2 uops perform multiple loads + let ResourceCycles = [1,2,1,1]; +} +def: InstRW<[ICXWriteGatherEVEX2], (instrs VGATHERQPSZ128rm, VPGATHERQDZ128rm, + VGATHERDPDZ128rm, VPGATHERDQZ128rm, + VGATHERQPDZ128rm, VPGATHERQQZ128rm)>; + +def ICXWriteGatherEVEX4 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort015,ICXPort0156]> { + let Latency = 19; + let NumMicroOps = 5; // 2 uops perform multiple loads + let ResourceCycles = [1,4,1,1]; +} +def: InstRW<[ICXWriteGatherEVEX4], (instrs VGATHERQPSZ256rm, VPGATHERQDZ256rm, + VGATHERQPDZ256rm, VPGATHERQQZ256rm, + VGATHERDPSZ128rm, VPGATHERDDZ128rm, + VGATHERDPDZ256rm, VPGATHERDQZ256rm)>; + +def ICXWriteGatherEVEX8 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort015,ICXPort0156]> { + let Latency = 21; + let NumMicroOps = 5; // 2 uops perform multiple loads + let ResourceCycles = [1,8,1,1]; +} +def: InstRW<[ICXWriteGatherEVEX8], (instrs VGATHERDPSZ256rm, VPGATHERDDZ256rm, + VGATHERDPDZrm, VPGATHERDQZrm, + VGATHERQPDZrm, VPGATHERQQZrm, + VGATHERQPSZrm, VPGATHERQDZrm)>; + +def ICXWriteGatherEVEX16 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort015,ICXPort0156]> { + let Latency = 25; + let NumMicroOps = 5; // 2 uops perform multiple loads + let ResourceCycles = [1,16,1,1]; +} +def: InstRW<[ICXWriteGatherEVEX16], (instrs VGATHERDPSZrm, VPGATHERDDZrm)>; + +def ICXWriteResGroup219 : SchedWriteRes<[ICXPort4,ICXPort5,ICXPort6,ICXPort23,ICXPort237,ICXPort06,ICXPort0156]> { + let Latency = 20; + let NumMicroOps = 8; + let ResourceCycles = [1,1,1,1,1,1,2]; +} +def: InstRW<[ICXWriteResGroup219], (instrs INSB, INSL, INSW)>; + +def ICXWriteResGroup220 : SchedWriteRes<[ICXPort5,ICXPort6,ICXPort0156]> { + let Latency = 20; + let NumMicroOps = 10; + let ResourceCycles = [1,2,7]; +} +def: InstRW<[ICXWriteResGroup220], (instrs MWAITrr)>; + +def ICXWriteResGroup222 : SchedWriteRes<[ICXPort0,ICXPort23,ICXFPDivider]> { + let Latency = 21; + let NumMicroOps = 2; + let ResourceCycles = [1,1,8]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def ICXWriteResGroup223 : SchedWriteRes<[ICXPort0,ICXPort23]> { + let Latency = 22; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[ICXWriteResGroup223], (instregex "DIV_F(32|64)m")>; + +def ICXWriteResGroupVEX2 : SchedWriteRes<[ICXPort0, ICXPort23, ICXPort5, ICXPort015]> { + let Latency = 18; + let NumMicroOps = 5; // 2 uops perform multiple loads + let ResourceCycles = [1,2,1,1]; +} +def: InstRW<[ICXWriteResGroupVEX2], (instrs VGATHERDPDrm, VPGATHERDQrm, + VGATHERQPDrm, VPGATHERQQrm, + VGATHERQPSrm, VPGATHERQDrm)>; + +def ICXWriteResGroupVEX4 : SchedWriteRes<[ICXPort0, ICXPort23, ICXPort5, ICXPort015]> { + let Latency = 20; + let NumMicroOps = 5; // 2 uops peform multiple loads + let ResourceCycles = [1,4,1,1]; +} +def: InstRW<[ICXWriteResGroupVEX4], (instrs VGATHERDPDYrm, VPGATHERDQYrm, + VGATHERDPSrm, VPGATHERDDrm, + VGATHERQPDYrm, VPGATHERQQYrm, + VGATHERQPSYrm, VPGATHERQDYrm)>; + +def ICXWriteResGroupVEX8 : SchedWriteRes<[ICXPort0, ICXPort23, ICXPort5, ICXPort015]> { + let Latency = 22; + let NumMicroOps = 5; // 2 uops perform multiple loads + let ResourceCycles = [1,8,1,1]; +} +def: InstRW<[ICXWriteResGroupVEX8], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>; + +def ICXWriteResGroup225 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort015]> { + let Latency = 22; + let NumMicroOps = 14; + let ResourceCycles = [5,5,4]; +} +def: InstRW<[ICXWriteResGroup225], (instregex "VPCONFLICTDZ128rr", + "VPCONFLICTQZ256rr")>; + +def ICXWriteResGroup228 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort5,ICXPort23,ICXPort237,ICXPort06,ICXPort0156]> { + let Latency = 23; + let NumMicroOps = 19; + let ResourceCycles = [2,1,4,1,1,4,6]; +} +def: InstRW<[ICXWriteResGroup228], (instrs CMPXCHG16B)>; + +def ICXWriteResGroup233 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> { + let Latency = 25; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[ICXWriteResGroup233], (instregex "DIV_FI(16|32)m")>; + +def ICXWriteResGroup239 : SchedWriteRes<[ICXPort0,ICXPort23]> { + let Latency = 27; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[ICXWriteResGroup239], (instregex "DIVR_F(32|64)m")>; + +def ICXWriteResGroup242 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort23,ICXPort015]> { + let Latency = 29; + let NumMicroOps = 15; + let ResourceCycles = [5,5,1,4]; +} +def: InstRW<[ICXWriteResGroup242], (instregex "VPCONFLICTQZ256rm(b?)")>; + +def ICXWriteResGroup243 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> { + let Latency = 30; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[ICXWriteResGroup243], (instregex "DIVR_FI(16|32)m")>; + +def ICXWriteResGroup247 : SchedWriteRes<[ICXPort5,ICXPort6,ICXPort23,ICXPort06,ICXPort0156]> { + let Latency = 35; + let NumMicroOps = 23; + let ResourceCycles = [1,5,3,4,10]; +} +def: InstRW<[ICXWriteResGroup247], (instregex "IN(8|16|32)ri", + "IN(8|16|32)rr")>; + +def ICXWriteResGroup248 : SchedWriteRes<[ICXPort5,ICXPort6,ICXPort23,ICXPort237,ICXPort06,ICXPort0156]> { + let Latency = 35; + let NumMicroOps = 23; + let ResourceCycles = [1,5,2,1,4,10]; +} +def: InstRW<[ICXWriteResGroup248], (instregex "OUT(8|16|32)ir", + "OUT(8|16|32)rr")>; + +def ICXWriteResGroup249 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort015]> { + let Latency = 37; + let NumMicroOps = 21; + let ResourceCycles = [9,7,5]; +} +def: InstRW<[ICXWriteResGroup249], (instregex "VPCONFLICTDZ256rr", + "VPCONFLICTQZrr")>; + +def ICXWriteResGroup250 : SchedWriteRes<[ICXPort1,ICXPort6,ICXPort23,ICXPort0156]> { + let Latency = 37; + let NumMicroOps = 31; + let ResourceCycles = [1,8,1,21]; +} +def: InstRW<[ICXWriteResGroup250], (instregex "XRSTOR(64)?")>; + +def ICXWriteResGroup252 : SchedWriteRes<[ICXPort1,ICXPort4,ICXPort5,ICXPort6,ICXPort23,ICXPort237,ICXPort15,ICXPort0156]> { + let Latency = 40; + let NumMicroOps = 18; + let ResourceCycles = [1,1,2,3,1,1,1,8]; +} +def: InstRW<[ICXWriteResGroup252], (instrs VMCLEARm)>; + +def ICXWriteResGroup253 : SchedWriteRes<[ICXPort4,ICXPort6,ICXPort23,ICXPort237,ICXPort0156]> { + let Latency = 41; + let NumMicroOps = 39; + let ResourceCycles = [1,10,1,1,26]; +} +def: InstRW<[ICXWriteResGroup253], (instrs XSAVE64)>; + +def ICXWriteResGroup254 : SchedWriteRes<[ICXPort5,ICXPort0156]> { + let Latency = 42; + let NumMicroOps = 22; + let ResourceCycles = [2,20]; +} +def: InstRW<[ICXWriteResGroup254], (instrs RDTSCP)>; + +def ICXWriteResGroup255 : SchedWriteRes<[ICXPort4,ICXPort6,ICXPort23,ICXPort237,ICXPort0156]> { + let Latency = 42; + let NumMicroOps = 40; + let ResourceCycles = [1,11,1,1,26]; +} +def: InstRW<[ICXWriteResGroup255], (instrs XSAVE)>; +def: InstRW<[ICXWriteResGroup255], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>; + +def ICXWriteResGroup256 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort23,ICXPort015]> { + let Latency = 44; + let NumMicroOps = 22; + let ResourceCycles = [9,7,1,5]; +} +def: InstRW<[ICXWriteResGroup256], (instregex "VPCONFLICTDZ256rm(b?)", + "VPCONFLICTQZrm(b?)")>; + +def ICXWriteResGroup258 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort05,ICXPort06,ICXPort0156]> { + let Latency = 62; + let NumMicroOps = 64; + let ResourceCycles = [2,8,5,10,39]; +} +def: InstRW<[ICXWriteResGroup258], (instrs FLDENVm)>; + +def ICXWriteResGroup259 : SchedWriteRes<[ICXPort0,ICXPort6,ICXPort23,ICXPort05,ICXPort06,ICXPort15,ICXPort0156]> { + let Latency = 63; + let NumMicroOps = 88; + let ResourceCycles = [4,4,31,1,2,1,45]; +} +def: InstRW<[ICXWriteResGroup259], (instrs FXRSTOR64)>; + +def ICXWriteResGroup260 : SchedWriteRes<[ICXPort0,ICXPort6,ICXPort23,ICXPort05,ICXPort06,ICXPort15,ICXPort0156]> { + let Latency = 63; + let NumMicroOps = 90; + let ResourceCycles = [4,2,33,1,2,1,47]; +} +def: InstRW<[ICXWriteResGroup260], (instrs FXRSTOR)>; + +def ICXWriteResGroup261 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort015]> { + let Latency = 67; + let NumMicroOps = 35; + let ResourceCycles = [17,11,7]; +} +def: InstRW<[ICXWriteResGroup261], (instregex "VPCONFLICTDZrr")>; + +def ICXWriteResGroup262 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort23,ICXPort015]> { + let Latency = 74; + let NumMicroOps = 36; + let ResourceCycles = [17,11,1,7]; +} +def: InstRW<[ICXWriteResGroup262], (instregex "VPCONFLICTDZrm(b?)")>; + +def ICXWriteResGroup263 : SchedWriteRes<[ICXPort5,ICXPort05,ICXPort0156]> { + let Latency = 75; + let NumMicroOps = 15; + let ResourceCycles = [6,3,6]; +} +def: InstRW<[ICXWriteResGroup263], (instrs FNINIT)>; + +def ICXWriteResGroup266 : SchedWriteRes<[ICXPort0,ICXPort1,ICXPort4,ICXPort5,ICXPort6,ICXPort237,ICXPort06,ICXPort0156]> { + let Latency = 106; + let NumMicroOps = 100; + let ResourceCycles = [9,1,11,16,1,11,21,30]; +} +def: InstRW<[ICXWriteResGroup266], (instrs FSTENVm)>; + +def ICXWriteResGroup267 : SchedWriteRes<[ICXPort6,ICXPort0156]> { + let Latency = 140; + let NumMicroOps = 4; + let ResourceCycles = [1,3]; +} +def: InstRW<[ICXWriteResGroup267], (instrs PAUSE)>; + +def: InstRW<[WriteZero], (instrs CLC)>; + + +// Instruction variants handled by the renamer. These might not need execution +// ports in certain conditions. +// See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs", +// section "Skylake Pipeline" > "Register allocation and renaming". +// These can be investigated with llvm-exegesis, e.g. +// echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=- +// echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=- + +def ICXWriteZeroLatency : SchedWriteRes<[]> { + let Latency = 0; +} + +def ICXWriteZeroIdiom : SchedWriteVariant<[ + SchedVar, [ICXWriteZeroLatency]>, + SchedVar +]>; +def : InstRW<[ICXWriteZeroIdiom], (instrs SUB32rr, SUB64rr, + XOR32rr, XOR64rr)>; + +def ICXWriteFZeroIdiom : SchedWriteVariant<[ + SchedVar, [ICXWriteZeroLatency]>, + SchedVar +]>; +def : InstRW<[ICXWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, + XORPDrr, VXORPDrr, + VXORPSZ128rr, + VXORPDZ128rr)>; + +def ICXWriteFZeroIdiomY : SchedWriteVariant<[ + SchedVar, [ICXWriteZeroLatency]>, + SchedVar +]>; +def : InstRW<[ICXWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr, + VXORPSZ256rr, VXORPDZ256rr)>; + +def ICXWriteFZeroIdiomZ : SchedWriteVariant<[ + SchedVar, [ICXWriteZeroLatency]>, + SchedVar +]>; +def : InstRW<[ICXWriteFZeroIdiomZ], (instrs VXORPSZrr, VXORPDZrr)>; + +def ICXWriteVZeroIdiomLogicX : SchedWriteVariant<[ + SchedVar, [ICXWriteZeroLatency]>, + SchedVar +]>; +def : InstRW<[ICXWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr, + VPXORDZ128rr, VPXORQZ128rr)>; + +def ICXWriteVZeroIdiomLogicY : SchedWriteVariant<[ + SchedVar, [ICXWriteZeroLatency]>, + SchedVar +]>; +def : InstRW<[ICXWriteVZeroIdiomLogicY], (instrs VPXORYrr, + VPXORDZ256rr, VPXORQZ256rr)>; + +def ICXWriteVZeroIdiomLogicZ : SchedWriteVariant<[ + SchedVar, [ICXWriteZeroLatency]>, + SchedVar +]>; +def : InstRW<[ICXWriteVZeroIdiomLogicZ], (instrs VPXORDZrr, VPXORQZrr)>; + +def ICXWriteVZeroIdiomALUX : SchedWriteVariant<[ + SchedVar, [ICXWriteZeroLatency]>, + SchedVar +]>; +def : InstRW<[ICXWriteVZeroIdiomALUX], (instrs PCMPGTBrr, VPCMPGTBrr, + PCMPGTDrr, VPCMPGTDrr, + PCMPGTWrr, VPCMPGTWrr)>; + +def ICXWriteVZeroIdiomALUY : SchedWriteVariant<[ + SchedVar, [ICXWriteZeroLatency]>, + SchedVar +]>; +def : InstRW<[ICXWriteVZeroIdiomALUY], (instrs VPCMPGTBYrr, + VPCMPGTDYrr, + VPCMPGTWYrr)>; + +def ICXWritePSUB : SchedWriteRes<[ICXPort015]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} + +def ICXWriteVZeroIdiomPSUB : SchedWriteVariant<[ + SchedVar, [ICXWriteZeroLatency]>, + SchedVar +]>; + +def : InstRW<[ICXWriteVZeroIdiomPSUB], (instrs PSUBBrr, VPSUBBrr, VPSUBBZ128rr, + PSUBDrr, VPSUBDrr, VPSUBDZ128rr, + PSUBQrr, VPSUBQrr, VPSUBQZ128rr, + PSUBWrr, VPSUBWrr, VPSUBWZ128rr, + VPSUBBYrr, VPSUBBZ256rr, + VPSUBDYrr, VPSUBDZ256rr, + VPSUBQYrr, VPSUBQZ256rr, + VPSUBWYrr, VPSUBWZ256rr, + VPSUBBZrr, + VPSUBDZrr, + VPSUBQZrr, + VPSUBWZrr)>; +def ICXWritePCMPGTQ : SchedWriteRes<[ICXPort5]> { + let Latency = 3; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} + +def ICXWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[ + SchedVar, [ICXWriteZeroLatency]>, + SchedVar +]>; +def : InstRW<[ICXWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr, + VPCMPGTQYrr)>; + + +// CMOVs that use both Z and C flag require an extra uop. +def ICXWriteCMOVA_CMOVBErr : SchedWriteRes<[ICXPort06]> { + let Latency = 2; + let ResourceCycles = [2]; + let NumMicroOps = 2; +} + +def ICXWriteCMOVA_CMOVBErm : SchedWriteRes<[ICXPort23,ICXPort06]> { + let Latency = 7; + let ResourceCycles = [1,2]; + let NumMicroOps = 3; +} + +def ICXCMOVA_CMOVBErr : SchedWriteVariant<[ + SchedVar, [ICXWriteCMOVA_CMOVBErr]>, + SchedVar +]>; + +def ICXCMOVA_CMOVBErm : SchedWriteVariant<[ + SchedVar, [ICXWriteCMOVA_CMOVBErm]>, + SchedVar +]>; + +def : InstRW<[ICXCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>; +def : InstRW<[ICXCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>; + +// SETCCs that use both Z and C flag require an extra uop. +def ICXWriteSETA_SETBEr : SchedWriteRes<[ICXPort06]> { + let Latency = 2; + let ResourceCycles = [2]; + let NumMicroOps = 2; +} + +def ICXWriteSETA_SETBEm : SchedWriteRes<[ICXPort4,ICXPort237,ICXPort06]> { + let Latency = 3; + let ResourceCycles = [1,1,2]; + let NumMicroOps = 4; +} + +def ICXSETA_SETBErr : SchedWriteVariant<[ + SchedVar, [ICXWriteSETA_SETBEr]>, + SchedVar +]>; + +def ICXSETA_SETBErm : SchedWriteVariant<[ + SchedVar, [ICXWriteSETA_SETBEm]>, + SchedVar +]>; + +def : InstRW<[ICXSETA_SETBErr], (instrs SETCCr)>; +def : InstRW<[ICXSETA_SETBErm], (instrs SETCCm)>; + +} // SchedModel -- 2.7.4