From 9e2d100e5322c52e29280c96bbb5609ca5af1539 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Mon, 5 Jun 2023 21:33:10 -0700 Subject: [PATCH] [AArch64,AVR,PowerPC] Migrate to new encodeInstruction that uses SmallVectorImpl. NFC Similar to 49488490d195591bfc90daef111cd7293f8c80aa. --- llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp | 8 +++++--- llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp | 9 +++++---- llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.h | 4 ++-- llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp | 9 +++++---- llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h | 2 +- 5 files changed, 18 insertions(+), 14 deletions(-) diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp index e482ab7..2dbbab1 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp @@ -171,7 +171,7 @@ public: unsigned fixMOVZ(const MCInst &MI, unsigned EncodedValue, const MCSubtargetInfo &STI) const; - void encodeInstruction(const MCInst &MI, raw_ostream &OS, + void encodeInstruction(const MCInst &MI, SmallVectorImpl &CB, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const override; @@ -661,7 +661,9 @@ unsigned AArch64MCCodeEmitter::fixMOVZ(const MCInst &MI, unsigned EncodedValue, return EncodedValue; } -void AArch64MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, +void AArch64MCCodeEmitter::encodeInstruction(const MCInst &MI, + SmallVectorImpl &CB, + SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { if (MI.getOpcode() == AArch64::TLSDESCCALL) { @@ -683,7 +685,7 @@ void AArch64MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, } uint64_t Binary = getBinaryCodeForInstr(MI, Fixups, STI); - support::endian::write(OS, Binary, support::little); + support::endian::write(CB, Binary, support::little); ++MCNumEmitted; // Keep track of the # of mi's emitted. } diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp b/llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp index 9edd8bb..d71ec08 100644 --- a/llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp +++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp @@ -272,16 +272,17 @@ unsigned AVRMCCodeEmitter::getMachineOpValue(const MCInst &MI, void AVRMCCodeEmitter::emitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI, - raw_ostream &OS) const { + SmallVectorImpl &CB) const { size_t WordCount = Size / 2; for (int64_t i = WordCount - 1; i >= 0; --i) { uint16_t Word = (Val >> (i * 16)) & 0xFFFF; - support::endian::write(OS, Word, support::endianness::little); + support::endian::write(CB, Word, support::endianness::little); } } -void AVRMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, +void AVRMCCodeEmitter::encodeInstruction(const MCInst &MI, + SmallVectorImpl &CB, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); @@ -292,7 +293,7 @@ void AVRMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, assert(Size > 0 && "Instruction size cannot be zero"); uint64_t BinaryOpCode = getBinaryCodeForInstr(MI, Fixups, STI); - emitInstruction(BinaryOpCode, Size, STI, OS); + emitInstruction(BinaryOpCode, Size, STI, CB); } MCCodeEmitter *createAVRMCCodeEmitter(const MCInstrInfo &MCII, diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.h b/llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.h index 1bfa79f..47bdf48 100644 --- a/llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.h +++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.h @@ -96,9 +96,9 @@ private: const MCSubtargetInfo &STI) const; void emitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI, - raw_ostream &OS) const; + SmallVectorImpl &CB) const; - void encodeInstruction(const MCInst &MI, raw_ostream &OS, + void encodeInstruction(const MCInst &MI, SmallVectorImpl &CB, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const override; diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp index e9e8c7b..da0174c 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp @@ -407,7 +407,8 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO, return MO.getImm(); } -void PPCMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, +void PPCMCCodeEmitter::encodeInstruction(const MCInst &MI, + SmallVectorImpl &CB, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI); @@ -419,13 +420,13 @@ void PPCMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, case 0: break; case 4: - support::endian::write(OS, Bits, E); + support::endian::write(CB, Bits, E); break; case 8: // If we emit a pair of instructions, the first one is // always in the top 32 bits, even on little-endian. - support::endian::write(OS, Bits >> 32, E); - support::endian::write(OS, Bits, E); + support::endian::write(CB, Bits >> 32, E); + support::endian::write(CB, Bits, E); break; default: llvm_unreachable("Invalid instruction size"); diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h index bab815b..17a15ef 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h @@ -112,7 +112,7 @@ public: SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; - void encodeInstruction(const MCInst &MI, raw_ostream &OS, + void encodeInstruction(const MCInst &MI, SmallVectorImpl &CB, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const override; -- 2.7.4